arm64: zynqmp: Update MALI 400 interrupt and clock names
authorParth Gajjar <parth.gajjar@amd.com>
Mon, 10 Jul 2023 12:37:29 +0000 (14:37 +0200)
committerMichal Simek <michal.simek@amd.com>
Fri, 21 Jul 2023 07:00:38 +0000 (09:00 +0200)
Motivation for the commit is to utilize the upstream community
device tree so that the either modified ARM Mali 400 driver
or upstream lima driver can be used.

Signed-off-by: Parth Gajjar <parth.gajjar@amd.com>
Signed-off-by: Vishal Sagar <vishal.sagar@amd.com>
Link: https://lore.kernel.org/r/1678181001-2327-2-git-send-email-parth.gajjar@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/89d046a9da5638e8b4918f80f3245d73ea46f99f.1688992653.git.michal.simek@amd.com
arch/arm/dts/zynqmp-clk-ccf.dtsi
arch/arm/dts/zynqmp.dtsi

index 173e4bc..4d44924 100644 (file)
 };
 
 &gpu {
-       clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>;
+       clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;
 };
 
 &lpd_dma_chan1 {
index 5f1e163..38114d5 100644 (file)
 
                gpu: gpu@fd4b0000 {
                        status = "disabled";
-                       compatible = "arm,mali-400", "arm,mali-utgard";
+                       compatible = "xlnx,zynqmp-mali", "arm,mali-400";
                        reg = <0x0 0xfd4b0000 0x0 0x10000>;
                        interrupt-parent = <&gic>;
                        interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
-                       interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
-                       clock-names = "gpu", "gpu_pp0", "gpu_pp1";
+                       interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
+                       clock-names = "bus", "core";
                        power-domains = <&zynqmp_firmware PD_GPU>;
                };