intel: Add support for RPLP
authorTejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Thu, 21 Apr 2022 17:04:52 +0000 (22:34 +0530)
committerRaviteja Goud Talla <ravitejax.goud.talla@intel.com>
Thu, 21 Apr 2022 17:34:33 +0000 (23:04 +0530)
Add RPLP platform support and PCIIDs

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Raviteja Goud Talla <ravitejax.goud.talla@intel.com>
intel/i915_pciids.h
intel/intel_chipset.c

index 8076d40..3301772 100644 (file)
        INTEL_VGA_DEVICE(0x46C2, info), \
        INTEL_VGA_DEVICE(0x46C3, info)
 
+/* RPL-P */
+#define INTEL_RPLP_IDS(info) \
+       INTEL_VGA_DEVICE(0xA720, info), \
+       INTEL_VGA_DEVICE(0xA721, info), \
+       INTEL_VGA_DEVICE(0xA7A0, info), \
+       INTEL_VGA_DEVICE(0xA7A1, info), \
+       INTEL_VGA_DEVICE(0xA7A8, info), \
+       INTEL_VGA_DEVICE(0xA7A9, info)
+
 /* ADL-N */
 #define INTEL_ADLN_IDS(info) \
        INTEL_VGA_DEVICE(0x46D0, info), \
index 99ad04a..ee8866c 100644 (file)
@@ -35,9 +35,10 @@ static const struct pci_device {
        uint16_t gen;
 } pciids[] = {
        /* Keep ids sorted by gen; latest gen first */
-       INTEL_RPLS_IDS(12),
        INTEL_ADLN_IDS(12),
+       INTEL_RPLP_IDS(12),
        INTEL_ADLP_IDS(12),
+       INTEL_RPLS_IDS(12),
        INTEL_ADLS_IDS(12),
        INTEL_RKL_IDS(12),
        INTEL_DG1_IDS(12),