};
struct hisi_pcie {
- struct pcie_port pp; /* pp.dbi_base is DT rc_dbi */
+ struct dw_pcie *pci;
struct regmap *subctrl;
u32 port_id;
- struct pcie_soc_ops *soc_ops;
+ const struct pcie_soc_ops *soc_ops;
};
/* HipXX PCIe host only supports 32-bit config access */
static int hisi_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
+ struct dw_pcie *pci;
struct hisi_pcie *hisi_pcie;
- const struct of_device_id *match;
- struct pcie_port *pp;
struct resource *reg;
struct device_driver *driver;
int ret;
if (!hisi_pcie)
return -ENOMEM;
- pp = &hisi_pcie->pp;
- pp->dev = dev;
+ pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
+ if (!pci)
+ return -ENOMEM;
+
+ pci->dev = dev;
+ pci->ops = &dw_pcie_ops;
+
driver = dev->driver;
- match = of_match_device(driver->of_match_table, dev);
- hisi_pcie->soc_ops = (struct pcie_soc_ops *) match->data;
+ hisi_pcie->soc_ops = of_device_get_match_data(dev);
hisi_pcie->subctrl =
- syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl");
+ syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl");
if (IS_ERR(hisi_pcie->subctrl)) {
dev_err(dev, "cannot get subctrl base\n");
return PTR_ERR(hisi_pcie->subctrl);