drm/amdgpu: add bitmask to iterate vmhubs

As the layout of VMHUB definition has been changed to cover multiple
XCD/AID case, the original num_vmhubs is not appropriate to do vmhub
iteration any more.

Drop num_vmhubs and introduce vmhubs_mask instead.

v2: switch to the new VMHUB layout
v3: use DECLARE_BITMAP to define vmhubs_mask

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 957b18b..0f163d2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -829,7 +829,7 @@ struct amdgpu_device {
        dma_addr_t                      dummy_page_addr;
        struct amdgpu_vm_manager        vm_manager;
        struct amdgpu_vmhub             vmhub[AMDGPU_MAX_VMHUBS];
-       unsigned                        num_vmhubs;
+       DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS);
 
        /* memory management */
        struct amdgpu_mman              mman;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index f0a136d..5afbcc3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -733,7 +733,7 @@ int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev,
        if (adev->family == AMDGPU_FAMILY_AI) {
                int i;
 
-               for (i = 0; i < adev->num_vmhubs; i++)
+               for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)
                        amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
        } else {
                amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 0);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index 01cb89f..6b12f4a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -182,7 +182,7 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
        }
        mb();
        amdgpu_device_flush_hdp(adev, NULL);
-       for (i = 0; i < adev->num_vmhubs; i++)
+       for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)
                amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
 
        drm_dev_exit(idx);
@@ -264,7 +264,7 @@ void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev)
 
        mb();
        amdgpu_device_flush_hdp(adev, NULL);
-       for (i = 0; i < adev->num_vmhubs; i++)
+       for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)
                amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
 }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index ea2a448..ff96f11 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -460,7 +460,7 @@ static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
                                &queried_pasid);
                if (ret && queried_pasid == pasid) {
                        if (all_hub) {
-                               for (i = 0; i < adev->num_vmhubs; i++)
+                               for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)
                                        gmc_v10_0_flush_gpu_tlb(adev, vmid,
                                                        i, flush_type);
                        } else {
@@ -928,7 +928,8 @@ static int gmc_v10_0_sw_init(void *handle)
        case IP_VERSION(10, 3, 6):
        case IP_VERSION(10, 3, 3):
        case IP_VERSION(10, 3, 7):
-               adev->num_vmhubs = 2;
+               set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
+               set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
                /*
                 * To fulfill 4-level page support,
                 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index fb2ac31..3453f1c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -364,7 +364,7 @@ static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
                                &queried_pasid);
                if (ret && queried_pasid == pasid) {
                        if (all_hub) {
-                               for (i = 0; i < adev->num_vmhubs; i++)
+                               for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)
                                        gmc_v11_0_flush_gpu_tlb(adev, vmid,
                                                        i, flush_type);
                        } else {
@@ -779,7 +779,8 @@ static int gmc_v11_0_sw_init(void *handle)
        case IP_VERSION(11, 0, 2):
        case IP_VERSION(11, 0, 3):
        case IP_VERSION(11, 0, 4):
-               adev->num_vmhubs = 2;
+               set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
+               set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
                /*
                 * To fulfill 4-level page support,
                 * vm size is 256TB (48bit), maximum size,

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index b7dad4e..aa754c9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -808,7 +808,7 @@ static int gmc_v6_0_sw_init(void *handle)
        int r;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-       adev->num_vmhubs = 1;
+       set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
 
        if (adev->flags & AMD_IS_APU) {
                adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 402960b..81609a2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -977,7 +977,7 @@ static int gmc_v7_0_sw_init(void *handle)
        int r;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-       adev->num_vmhubs = 1;
+       set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
 
        if (adev->flags & AMD_IS_APU) {
                adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 504c1b3..d48e337 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1093,7 +1093,7 @@ static int gmc_v8_0_sw_init(void *handle)
        int r;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-       adev->num_vmhubs = 1;
+       set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
 
        if (adev->flags & AMD_IS_APU) {
                adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 193ba4d..d4bfb5f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -481,7 +481,7 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 
        switch (state) {
        case AMDGPU_IRQ_STATE_DISABLE:
-               for (j = 0; j < adev->num_vmhubs; j++) {
+               for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
                        hub = &adev->vmhub[j];
                        for (i = 0; i < 16; i++) {
                                reg = hub->vm_context0_cntl + i;
@@ -509,7 +509,7 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
                }
                break;
        case AMDGPU_IRQ_STATE_ENABLE:
-               for (j = 0; j < adev->num_vmhubs; j++) {
+               for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
                        hub = &adev->vmhub[j];
                        for (i = 0; i < 16; i++) {
                                reg = hub->vm_context0_cntl + i;
@@ -803,7 +803,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
        u32 j, inv_req, inv_req2, tmp;
        struct amdgpu_vmhub *hub;
 
-       BUG_ON(vmhub >= adev->num_vmhubs);
+       BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS);
 
        hub = &adev->vmhub[vmhub];
        if (adev->gmc.xgmi.num_physical_nodes &&
@@ -987,7 +987,7 @@ static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
                                &queried_pasid);
                if (ret && queried_pasid == pasid) {
                        if (all_hub) {
-                               for (i = 0; i < adev->num_vmhubs; i++)
+                               for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)
                                        gmc_v9_0_flush_gpu_tlb(adev, vmid,
                                                        i, flush_type);
                        } else {
@@ -1684,7 +1684,8 @@ static int gmc_v9_0_sw_init(void *handle)
        switch (adev->ip_versions[GC_HWIP][0]) {
        case IP_VERSION(9, 1, 0):
        case IP_VERSION(9, 2, 2):
-               adev->num_vmhubs = 2;
+               set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
+               set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
 
                if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
                        amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
@@ -1701,8 +1702,8 @@ static int gmc_v9_0_sw_init(void *handle)
        case IP_VERSION(9, 3, 0):
        case IP_VERSION(9, 4, 2):
        case IP_VERSION(9, 4, 3):
-               adev->num_vmhubs = 2;
-
+               set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
+               set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
 
                /*
                 * To fulfill 4-level page support,
@@ -1718,7 +1719,9 @@ static int gmc_v9_0_sw_init(void *handle)
                        adev->gmc.translate_further = adev->vm_manager.num_level > 1;
                break;
        case IP_VERSION(9, 4, 1):
-               adev->num_vmhubs = 3;
+               set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
+               set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
+               set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask);
 
                /* Keep the vm size same with Vega20 */
                amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
@@ -1944,7 +1947,7 @@ static int gmc_v9_0_hw_init(void *handle)
                        adev->gfxhub.funcs->set_fault_enable_default(adev, value);
                adev->mmhub.funcs->set_fault_enable_default(adev, value);
        }
-       for (i = 0; i < adev->num_vmhubs; ++i) {
+       for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
                if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0)))
                        continue;
                gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);