radv: Expose VK_KHR_workgroup_memory_explicit_layout.
authorBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fri, 6 Nov 2020 23:38:39 +0000 (00:38 +0100)
committerBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Thu, 28 Jan 2021 23:05:36 +0000 (00:05 +0100)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8752>

docs/relnotes/new_features.txt
src/amd/vulkan/radv_device.c
src/amd/vulkan/radv_extensions.py
src/amd/vulkan/radv_shader.c

index 9bb20c6..e08d5ee 100644 (file)
@@ -13,4 +13,4 @@ Panfrost g31/g52/g72 exposes ES 3.0
 Panfrost t760+ exposes GL 3.1 (including on Bifrost)
 Sparse memory support on RADV
 Rapid packed math (16bit-vectorization) on RADV
-VK_KHR_workgroup_memory_explicit_layout on Intel
+VK_KHR_workgroup_memory_explicit_layout on Intel, RADV
index 2a06fc3..7353fb4 100644 (file)
@@ -1509,6 +1509,15 @@ void radv_GetPhysicalDeviceFeatures2(
                        features->attachmentFragmentShadingRate = false; /* TODO */
                        break;
                }
+               case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_WORKGROUP_MEMORY_EXPLICIT_LAYOUT_FEATURES_KHR: {
+                       VkPhysicalDeviceWorkgroupMemoryExplicitLayoutFeaturesKHR *features =
+                               (VkPhysicalDeviceWorkgroupMemoryExplicitLayoutFeaturesKHR *)ext;
+                       features->workgroupMemoryExplicitLayout = true;
+                       features->workgroupMemoryExplicitLayoutScalarBlockLayout = true;
+                       features->workgroupMemoryExplicitLayout8BitAccess = true;
+                       features->workgroupMemoryExplicitLayout16BitAccess = true;
+                       break;
+               }
                default:
                        break;
                }
index 16ccdee..ddc9278 100644 (file)
@@ -116,6 +116,7 @@ EXTENSIONS = [
     Extension('VK_KHR_variable_pointers',                 1, True),
     Extension('VK_KHR_vulkan_memory_model',               3, True),
     Extension('VK_KHR_wayland_surface',                   6, 'VK_USE_PLATFORM_WAYLAND_KHR'),
+    Extension('VK_KHR_workgroup_memory_explicit_layout',  1, True),
     Extension('VK_KHR_xcb_surface',                       6, 'VK_USE_PLATFORM_XCB_KHR'),
     Extension('VK_KHR_xlib_surface',                      6, 'VK_USE_PLATFORM_XLIB_KHR'),
     Extension('VK_EXT_4444_formats',                      1, True),
index 3ecb8cb..70ba75a 100644 (file)
@@ -493,6 +493,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
                                .vk_memory_model = true,
                                .vk_memory_model_device_scope = true,
                                .fragment_shading_rate = device->physical_device->rad_info.chip_class >= GFX10_3,
+                               .workgroup_memory_explicit_layout = true,
                        },
                        .ubo_addr_format = nir_address_format_32bit_index_offset,
                        .ssbo_addr_format = nir_address_format_32bit_index_offset,
@@ -679,8 +680,10 @@ radv_shader_compile_to_nir(struct radv_device *device,
 
        /* Lower deref operations for compute shared memory. */
        if (nir->info.stage == MESA_SHADER_COMPUTE) {
-               NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
-                          nir_var_mem_shared, shared_var_info);
+               if (!nir->info.cs.shared_memory_explicit_layout) {
+                       NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
+                                  nir_var_mem_shared, shared_var_info);
+               }
                NIR_PASS_V(nir, nir_lower_explicit_io,
                           nir_var_mem_shared, nir_address_format_32bit_offset);
        }