2011-03-06 Andrew Stubbs <ams@codesourcery.com>

	    Julian Brown  <julian@codesourcery.com>
	    Mark Shinwell  <shinwell@codesourcery.com>

	gcc/
	* config/arm/arm.h (arm_class_likely_spilled_p): Check against
	LO_REGS only for Thumb-1.
	(MODE_BASE_REG_CLASS): Restrict base registers to those which can
	be used in short instructions when optimising for size on Thumb-2.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@172032 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a8f8661..a747d60 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2011-03-06  Andrew Stubbs  <ams@codesourcery.com>
+           Julian Brown  <julian@codesourcery.com>
+           Mark Shinwell  <shinwell@codesourcery.com>
+
+       * config/arm/arm.h (arm_class_likely_spilled_p): Check against
+       LO_REGS only for Thumb-1.
+       (MODE_BASE_REG_CLASS): Restrict base registers to those which can
+       be used in short instructions when optimising for size on Thumb-2.
+
 2011-04-06  Eric Botcazou  <ebotcazou@adacore.com>
 
        * gimple-low.c (lower_gimple_return): When not optimizing, force labels

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 4fee4da..533ad91 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -22333,14 +22333,16 @@ arm_preferred_simd_mode (enum machine_mode mode)
 
 /* Implement TARGET_CLASS_LIKELY_SPILLED_P.
  
-   We need to define this for LO_REGS on thumb.  Otherwise we can end up
-   using r0-r4 for function arguments, r7 for the stack frame and don't
-   have enough left over to do doubleword arithmetic.  */
-
+   We need to define this for LO_REGS on Thumb-1.  Otherwise we can end up
+   using r0-r4 for function arguments, r7 for the stack frame and don't have
+   enough left over to do doubleword arithmetic.  For Thumb-2 all the
+   potentially problematic instructions accept high registers so this is not
+   necessary.  Care needs to be taken to avoid adding new Thumb-2 patterns
+   that require many low registers.  */
 static bool
 arm_class_likely_spilled_p (reg_class_t rclass)
 {
-  if ((TARGET_THUMB && rclass == LO_REGS)
+  if ((TARGET_THUMB1 && rclass == LO_REGS)
       || rclass  == CC_REG)
     return true;
 

diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index f302de2..580f2de 100644 (file)
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1165,7 +1165,7 @@ enum reg_class
    when addressing quantities in QI or HI mode; if we don't know the
    mode, then we must be conservative.  */
 #define MODE_BASE_REG_CLASS(MODE)                                      \
-    (TARGET_32BIT ? CORE_REGS :                                        \
+    (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS :      \
      (((MODE) == SImode) ? BASE_REGS : LO_REGS))
 
 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS