dm: core: Switch order of pinctrl and power domain calls
authorMichal Simek <michal.simek@xilinx.com>
Fri, 7 Jan 2022 15:38:09 +0000 (16:38 +0100)
committerSimon Glass <sjg@chromium.org>
Thu, 13 Jan 2022 16:13:41 +0000 (09:13 -0700)
The commit 3ad307784847 ("dm: core: device: enable power domain in probe")
introduced enabling power domain when device is probed.
By checking this sequence in Linux kernel was found that power domain is
handled first followed by pinctrl setting.

This patch is switching this order to follow Linux kernel that power
domains are handled first follow by pinctrl setting.

The issue was found on Xilinx Kria SOM where firmware is blocking setting
up pin configuration/muxes without enabling power domain for the specific
IP first.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
drivers/core/device.c

index 4873c47..d917d4e 100644 (file)
@@ -518,6 +518,14 @@ int device_probe(struct udevice *dev)
 
        dev_or_flags(dev, DM_FLAG_ACTIVATED);
 
+       if (CONFIG_IS_ENABLED(POWER_DOMAIN) && dev->parent &&
+           (device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN) &&
+           !(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF)) {
+               ret = dev_power_domain_on(dev);
+               if (ret)
+                       goto fail;
+       }
+
        /*
         * Process pinctrl for everything except the root device, and
         * continue regardless of the result of pinctrl. Don't process pinctrl
@@ -540,14 +548,6 @@ int device_probe(struct udevice *dev)
                                  dev->name, ret, errno_str(ret));
        }
 
-       if (CONFIG_IS_ENABLED(POWER_DOMAIN) && dev->parent &&
-           (device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN) &&
-           !(drv->flags & DM_FLAG_DEFAULT_PD_CTRL_OFF)) {
-               ret = dev_power_domain_on(dev);
-               if (ret)
-                       goto fail;
-       }
-
        if (CONFIG_IS_ENABLED(IOMMU) && dev->parent &&
            (device_get_uclass_id(dev) != UCLASS_IOMMU)) {
                ret = dev_iommu_enable(dev);