spi: cadence-quadspi: Abort read if dummy cycles required are too many

[ Upstream commit ceeda328edeeeeac7579e9dbf0610785a3b83d39 ]

The controller can only support up to 31 dummy cycles. If the command
requires more it falls back to using 31. This command is likely to fail
because the correct number of cycles are not waited upon. Rather than
silently issuing an incorrect command, fail loudly so the caller can get
a chance to find out the command can't be supported by the controller.

Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller")
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20201222184425.7028-3-p.yadav@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index ba7d40c2922f7ceffccd64ec2a6def928c6d2fd1..826b01f346246653d8d1213beb370f7308cf3959 100644 (file)
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -461,7 +461,7 @@ static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
        /* Setup dummy clock cycles */
        dummy_clk = op->dummy.nbytes * 8;
        if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
-               dummy_clk = CQSPI_DUMMY_CLKS_MAX;
+               return -EOPNOTSUPP;
 
        if (dummy_clk)
                reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)