testsuite: aarch64: Add fusion tests for FP vml[as] intrinsics

Add compilation tests to make sure that the output of vmla/vmls
floating-point Neon intrinsics (fmul, fadd/fsub) is not fused into
fmla/fmls instructions.

gcc/testsuite/ChangeLog:

2021-02-16  Jonathan Wright  <jonathan.wright@arm.com>

	* gcc.target/aarch64/advsimd-intrinsics/vmla_float_not_fused.c:
	New test.
	* gcc.target/aarch64/advsimd-intrinsics/vmls_float_not_fused.c:
	New test.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_float_not_fused.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_float_not_fused.c
new file mode 100644 (file)
index 0000000..b14b259
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_float_not_fused.c
@@ -0,0 +1,67 @@
+/* { dg-skip-if "" { arm*-*-* } } */
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+
+#include <arm_neon.h>
+
+float32x2_t foo_f32 (float32x2_t a, float32x2_t b, float32x2_t c)
+{
+  return vmla_f32 (a, b, c);
+}
+
+float32x4_t fooq_f32 (float32x4_t a, float32x4_t b, float32x4_t c)
+{
+  return vmlaq_f32 (a, b, c);
+}
+
+float32x2_t foo_n_f32 (float32x2_t a, float32x2_t b, float32_t c)
+{
+  return vmla_n_f32 (a, b, c);
+}
+
+float32x4_t fooq_n_f32 (float32x4_t a, float32x4_t b, float32_t c)
+{
+  return vmlaq_n_f32 (a, b, c);
+}
+
+float32x2_t foo_lane_f32 (float32x2_t a,
+                         float32x2_t b,
+                         float32x2_t v)
+{
+  return vmla_lane_f32 (a, b, v, 0);
+}
+
+float32x4_t fooq_lane_f32 (float32x4_t a,
+                          float32x4_t b,
+                          float32x2_t v)
+{
+  return vmlaq_lane_f32 (a, b, v, 0);
+}
+
+float32x2_t foo_laneq_f32 (float32x2_t a,
+                          float32x2_t b,
+                          float32x4_t v)
+{
+  return vmla_laneq_f32 (a, b, v, 0);
+}
+
+float32x4_t fooq_laneq_f32 (float32x4_t a,
+                           float32x4_t b,
+                           float32x4_t v)
+{
+  return vmlaq_laneq_f32 (a, b, v, 0);
+}
+
+float64x1_t foo_f64 (float64x1_t a, float64x1_t b, float64x1_t c)
+{
+  return vmla_f64 (a, b, c);
+}
+
+float64x2_t fooq_f64 (float64x2_t a, float64x2_t b, float64x2_t c)
+{
+  return vmlaq_f64 (a, b, c);
+}
+
+/* { dg-final { scan-assembler-times {\tfmul\t} 10} }  */
+/* { dg-final { scan-assembler-times {\tfadd\t} 10} }  */

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_float_not_fused.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_float_not_fused.c
new file mode 100644 (file)
index 0000000..c6f62c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_float_not_fused.c
@@ -0,0 +1,67 @@
+/* { dg-skip-if "" { arm*-*-* } } */
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+
+#include <arm_neon.h>
+
+float32x2_t foo_f32 (float32x2_t a, float32x2_t b, float32x2_t c)
+{
+  return vmls_f32 (a, b, c);
+}
+
+float32x4_t fooq_f32 (float32x4_t a, float32x4_t b, float32x4_t c)
+{
+  return vmlsq_f32 (a, b, c);
+}
+
+float32x2_t foo_n_f32 (float32x2_t a, float32x2_t b, float32_t c)
+{
+  return vmls_n_f32 (a, b, c);
+}
+
+float32x4_t fooq_n_f32 (float32x4_t a, float32x4_t b, float32_t c)
+{
+  return vmlsq_n_f32 (a, b, c);
+}
+
+float32x2_t foo_lane_f32 (float32x2_t a,
+                         float32x2_t b,
+                         float32x2_t v)
+{
+  return vmls_lane_f32 (a, b, v, 0);
+}
+
+float32x4_t fooq_lane_f32 (float32x4_t a,
+                          float32x4_t b,
+                          float32x2_t v)
+{
+  return vmlsq_lane_f32 (a, b, v, 0);
+}
+
+float32x2_t foo_laneq_f32 (float32x2_t a,
+                          float32x2_t b,
+                          float32x4_t v)
+{
+  return vmls_laneq_f32 (a, b, v, 0);
+}
+
+float32x4_t fooq_laneq_f32 (float32x4_t a,
+                           float32x4_t b,
+                           float32x4_t v)
+{
+  return vmlsq_laneq_f32 (a, b, v, 0);
+}
+
+float64x1_t foo_f64 (float64x1_t a, float64x1_t b, float64x1_t c)
+{
+  return vmls_f64 (a, b, c);
+}
+
+float64x2_t fooq_f64 (float64x2_t a, float64x2_t b, float64x2_t c)
+{
+  return vmlsq_f64 (a, b, c);
+}
+
+/* { dg-final { scan-assembler-times {\tfmul\t} 10} }  */
+/* { dg-final { scan-assembler-times {\tfsub\t} 10} }  */