[RISCV] Add test cases to show missed opportunity to fold (sub C, (xor (setcc), 1...

(sub C, (xori X, 1)) can be folded to (add X, C-1) if X is 0 or 1.

This would avoid the xori and in some cases remove an instruction
neede to materialize the constant.

diff --git a/llvm/test/CodeGen/RISCV/double-select-fcmp.ll b/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
index a2344bb..43c70c6 100644 (file)
--- a/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-select-fcmp.ll
@@ -253,3 +253,28 @@ define i32 @select_fcmp_oeq_1_2(double %a, double %b) {
   %2 = select i1 %1, i32 1, i32 2
   ret i32 %2
 }
+
+define signext i32 @select_fcmp_uge_negone_zero(double %a, double %b) nounwind {
+; CHECK-LABEL: select_fcmp_uge_negone_zero:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.d a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %1 = fcmp ugt double %a, %b
+  %2 = select i1 %1, i32 -1, i32 0
+  ret i32 %2
+}
+
+define signext i32 @select_fcmp_uge_1_2(double %a, double %b) nounwind {
+; CHECK-LABEL: select_fcmp_uge_1_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.d a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    li a1, 2
+; CHECK-NEXT:    sub a0, a1, a0
+; CHECK-NEXT:    ret
+  %1 = fcmp ugt double %a, %b
+  %2 = select i1 %1, i32 1, i32 2
+  ret i32 %2
+}

diff --git a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
index 6d52d41..d320f3e 100644 (file)
--- a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
@@ -253,3 +253,28 @@ define i32 @select_fcmp_oeq_1_2(float %a, float %b) {
   %2 = select i1 %1, i32 1, i32 2
   ret i32 %2
 }
+
+define signext i32 @select_fcmp_uge_negone_zero(float %a, float %b) nounwind {
+; CHECK-LABEL: select_fcmp_uge_negone_zero:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %1 = fcmp ugt float %a, %b
+  %2 = select i1 %1, i32 -1, i32 0
+  ret i32 %2
+}
+
+define signext i32 @select_fcmp_uge_1_2(float %a, float %b) nounwind {
+; CHECK-LABEL: select_fcmp_uge_1_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.s a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    li a1, 2
+; CHECK-NEXT:    sub a0, a1, a0
+; CHECK-NEXT:    ret
+  %1 = fcmp ugt float %a, %b
+  %2 = select i1 %1, i32 1, i32 2
+  ret i32 %2
+}

diff --git a/llvm/test/CodeGen/RISCV/half-select-fcmp.ll b/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
index 5475ae4..92f2fdc 100644 (file)
--- a/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
@@ -253,3 +253,28 @@ define i32 @select_fcmp_oeq_1_2(half %a, half %b) {
   %2 = select i1 %1, i32 1, i32 2
   ret i32 %2
 }
+
+define signext i32 @select_fcmp_uge_negone_zero(half %a, half %b) nounwind {
+; CHECK-LABEL: select_fcmp_uge_negone_zero:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.h a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    ret
+  %1 = fcmp ugt half %a, %b
+  %2 = select i1 %1, i32 -1, i32 0
+  ret i32 %2
+}
+
+define signext i32 @select_fcmp_uge_1_2(half %a, half %b) nounwind {
+; CHECK-LABEL: select_fcmp_uge_1_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fle.h a0, fa0, fa1
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    li a1, 2
+; CHECK-NEXT:    sub a0, a1, a0
+; CHECK-NEXT:    ret
+  %1 = fcmp ugt half %a, %b
+  %2 = select i1 %1, i32 1, i32 2
+  ret i32 %2
+}