KVM: VMX: Skip filter updates for MSRs that KVM is already intercepting

When handling userspace MSR filter updates, recompute interception for
possible passthrough MSRs if and only if KVM wants to disabled
interception.  If KVM wants to intercept accesses, i.e. the associated
bit is set in vmx->shadow_msr_intercept, then there's no need to set the
intercept again as KVM will intercept the MSR regardless of userspace's
wants.

No functional change intended, the call to vmx_enable_intercept_for_msr()
really is just a gigantic nop.

Suggested-by: Aaron Lewis <aaronlewis@google.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20220610214140.612025-1-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 5e14e4c..61962f3 100644 (file)
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -3981,17 +3981,21 @@ static void vmx_msr_filter_changed(struct kvm_vcpu *vcpu)
        u32 i;
 
        /*
-        * Set intercept permissions for all potentially passed through MSRs
-        * again. They will automatically get filtered through the MSR filter,
-        * so we are back in sync after this.
+        * Redo intercept permissions for MSRs that KVM is passing through to
+        * the guest.  Disabling interception will check the new MSR filter and
+        * ensure that KVM enables interception if usersepace wants to filter
+        * the MSR.  MSRs that KVM is already intercepting don't need to be
+        * refreshed since KVM is going to intercept them regardless of what
+        * userspace wants.
         */
        for (i = 0; i < ARRAY_SIZE(vmx_possible_passthrough_msrs); i++) {
                u32 msr = vmx_possible_passthrough_msrs[i];
-               bool read = test_bit(i, vmx->shadow_msr_intercept.read);
-               bool write = test_bit(i, vmx->shadow_msr_intercept.write);
 
-               vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_R, read);
-               vmx_set_intercept_for_msr(vcpu, msr, MSR_TYPE_W, write);
+               if (!test_bit(i, vmx->shadow_msr_intercept.read))
+                       vmx_disable_intercept_for_msr(vcpu, msr, MSR_TYPE_R);
+
+               if (!test_bit(i, vmx->shadow_msr_intercept.write))
+                       vmx_disable_intercept_for_msr(vcpu, msr, MSR_TYPE_W);
        }
 
        pt_update_intercept_for_msr(vcpu);