* alpha.c (reg_not_elim_operand): New.

        * alpha.h (PREDICATE_CODES): Add it.
        * alpha.md (s48addq, s48subq patterns): Use it as the predicate
        for the multiplicand.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@23650 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 044c2f5..df3073f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+Fri Nov 13 22:19:23 1998  Richard Henderson  <rth@cygnus.com>
+
+       * alpha.c (reg_not_elim_operand): New.
+       * alpha.h (PREDICATE_CODES): Add it.
+       * alpha.md (s48addq, s48subq patterns): Use it as the predicate
+       for the multiplicand.
+
 Fri Nov 13 22:50:37 1998  David Edelsohn  <edelsohn@mhpcc.edu>
 
        * rs6000.md (movsf): Remove explicit secondary-reload-like

diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index 3de6f59..04a5c40 100644 (file)
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -833,6 +833,31 @@ any_memory_operand (op, mode)
              && REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER));
 }
 
+/* Returns 1 if OP is not an eliminable register.
+
+   This exists to cure a pathological abort in the s8addq (et al) patterns,
+
+       long foo () { long t; bar(); return (long) &t * 26107; }
+
+   which run afoul of a hack in reload to cure a (presumably) similar
+   problem with lea-type instructions on other targets.  But there is
+   one of us and many of them, so work around the problem by selectively
+   preventing combine from making the optimization.  */
+
+int
+reg_not_elim_operand (op, mode)
+      register rtx op;
+      enum machine_mode mode;
+{
+  rtx inner = op;
+  if (GET_CODE (op) == SUBREG)
+    inner = SUBREG_REG (op);
+  if (inner == frame_pointer_rtx || inner == arg_pointer_rtx)
+    return 0;
+
+  return register_operand (op, mode);
+}
+\f
 /* Return 1 if this function can directly return via $26.  */
 
 int

diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h
index 1105bca..13ce722 100644 (file)
--- a/gcc/config/alpha/alpha.h
+++ b/gcc/config/alpha/alpha.h
@@ -2293,7 +2293,8 @@ do {                                                                      \
   {"unaligned_memory_operand", {MEM}},                                 \
   {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}},                        \
   {"any_memory_operand", {MEM}},                                       \
-  {"hard_fp_register_operand", {SUBREG, REG}},
+  {"hard_fp_register_operand", {SUBREG, REG}},                         \
+  {"reg_not_elim_operand", {SUBREG, REG}},
 \f
 /* Tell collect that the object format is ECOFF.  */
 #define OBJECT_FORMAT_COFF
@@ -2484,6 +2485,7 @@ extern int divmod_operator ();
 extern int call_operand ();
 extern int reg_or_cint_operand ();
 extern int hard_fp_register_operand ();
+extern int reg_not_elim_operand ();
 extern void alpha_set_memflags ();
 extern int aligned_memory_operand ();
 extern void get_aligned_mem ();

diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index ebd03fc..b237eae 100644 (file)
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -484,7 +484,7 @@
        (sign_extend:DI
         (plus:SI (match_operand:SI 1 "register_operand" "")
                  (match_operand:SI 2 "const_int_operand" ""))))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
+   (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
   "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
    && INTVAL (operands[2]) % 4 == 0"
   [(set (match_dup 3) (match_dup 4))
@@ -554,24 +554,24 @@
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r,r")
-       (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,rJ")
+       (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
                          (match_operand:SI 2 "const48_operand" "I,I"))
                 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
   ""
   "@
-   s%2addl %r1,%3,%0
-   s%2subl %r1,%n3,%0")
+   s%2addl %1,%3,%0
+   s%2subl %1,%n3,%0")
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r,r")
        (sign_extend:DI
-        (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,rJ")
+        (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
                           (match_operand:SI 2 "const48_operand" "I,I"))
                  (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
   ""
   "@
-   s%2addl %r1,%3,%0
-   s%2subl %r1,%n3,%0")
+   s%2addl %1,%3,%0
+   s%2subl %1,%n3,%0")
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -581,7 +581,7 @@
                                               (match_operand 3 "" "")])
                           (match_operand:SI 4 "const48_operand" ""))
                  (match_operand:SI 5 "add_operand" ""))))
-   (clobber (match_operand:DI 6 "register_operand" ""))]
+   (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
   ""
   [(set (match_dup 6) (match_dup 7))
    (set (match_dup 0)
@@ -596,105 +596,14 @@
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r,r")
-       (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
+       (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
                          (match_operand:DI 2 "const48_operand" "I,I"))
                 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
   ""
   "@
-   s%2addq %r1,%3,%0
+   s%2addq %1,%3,%0
    s%2subq %1,%n3,%0")
 
-;; These variants of the above insns can occur if the third operand
-;; is the frame pointer.  This is a kludge, but there doesn't
-;; seem to be a way around it.  Only recognize them while reloading.
-
-(define_insn ""
-  [(set (match_operand:DI 0 "some_operand" "=&r")
-       (plus:DI (plus:DI (match_operand:DI 1 "some_operand" "r")
-                         (match_operand:DI 2 "some_operand" "r"))
-                (match_operand:DI 3 "some_operand" "rIOKL")))]
-  "reload_in_progress"
-  "#")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-       (plus:DI (plus:DI (match_operand:DI 1 "register_operand" "")
-                         (match_operand:DI 2 "register_operand" ""))
-                (match_operand:DI 3 "add_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
-  "")
-                                          
-(define_insn ""
-  [(set (match_operand:SI 0 "some_operand" "=&r")
-       (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "some_operand" "rJ")
-                                  (match_operand:SI 2 "const48_operand" "I"))
-                         (match_operand:SI 3 "some_operand" "r"))
-                (match_operand:SI 4 "some_operand" "rIOKL")))]
-  "reload_in_progress"
-  "#")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "r")
-       (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
-                                  (match_operand:SI 2 "const48_operand" ""))
-                         (match_operand:SI 3 "register_operand" ""))
-                (match_operand:SI 4 "add_operand" "rIOKL")))]
-  "reload_completed"
-  [(set (match_dup 0)
-       (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "some_operand" "=&r")
-       (sign_extend:DI
-        (plus:SI (plus:SI
-                  (mult:SI (match_operand:SI 1 "some_operand" "rJ")
-                           (match_operand:SI 2 "const48_operand" "I"))
-                  (match_operand:SI 3 "some_operand" "r"))
-                 (match_operand:SI 4 "some_operand" "rIOKL"))))]
-  "reload_in_progress"
-  "#")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-       (sign_extend:DI
-        (plus:SI (plus:SI
-                  (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
-                           (match_operand:SI 2 "const48_operand" ""))
-                  (match_operand:SI 3 "register_operand" ""))
-                 (match_operand:SI 4 "add_operand" ""))))]
-  "reload_completed"
-  [(set (match_dup 5)
-       (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 5) (match_dup 4))))]
-  "
-{ operands[5] = gen_lowpart (SImode, operands[0]);
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "some_operand" "=&r")
-       (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "some_operand" "rJ")
-                                  (match_operand:DI 2 "const48_operand" "I"))
-                         (match_operand:DI 3 "some_operand" "r"))
-                (match_operand:DI 4 "some_operand" "rIOKL")))]
-  "reload_in_progress"
-  "#")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "=")
-       (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "")
-                                  (match_operand:DI 2 "const48_operand" ""))
-                         (match_operand:DI 3 "register_operand" ""))
-                (match_operand:DI 4 "add_operand" "")))]
-  "reload_completed"
-  [(set (match_dup 0)
-       (plus:DI (mult:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
-  "")
-
 (define_insn "negsi2"
   [(set (match_operand:SI 0 "register_operand" "=r")
        (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
@@ -758,28 +667,28 @@
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
-       (minus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
+       (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
                           (match_operand:SI 2 "const48_operand" "I"))
                  (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
   ""
-  "s%2subl %r1,%3,%0")
+  "s%2subl %1,%3,%0")
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
        (sign_extend:DI
-        (minus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
+        (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
                            (match_operand:SI 2 "const48_operand" "I"))
                   (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
   ""
-  "s%2subl %r1,%3,%0")
+  "s%2subl %1,%3,%0")
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
-       (minus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
+       (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
                           (match_operand:DI 2 "const48_operand" "I"))
                  (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
   ""
-  "s%2subq %r1,%3,%0")
+  "s%2subq %1,%3,%0")
 
 (define_insn "mulsi3"
   [(set (match_operand:SI 0 "register_operand" "=r")