#elif defined(TARGET_PPC)
#if 0
if ((interrupt_request & CPU_INTERRUPT_RESET)) {
- cpu_ppc_reset(env);
+ cpu_reset(env);
}
#endif
if (interrupt_request & CPU_INTERRUPT_HARD) {
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
/* XXX: TOFIX */
#if 0
- cpu_ppc_reset(env);
+ cpu_reset(env);
#else
qemu_system_reset_request();
#endif
#if 0
/*****************************************************************************/
/* Handle system reset (for now, just stop emulation) */
-void cpu_ppc_reset (CPUState *env)
+void cpu_reset(CPUState *env)
{
printf("Reset asked... Stop emulation\n");
abort();
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
/* XXX: TOFIX */
#if 0
- cpu_ppc_reset(env);
+ cpu_reset(env);
#else
qemu_system_reset_request();
#endif
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
/* XXX: TOFIX */
#if 0
- cpu_ppc_reset(env);
+ cpu_reset(env);
#else
qemu_system_reset_request();
#endif
tb_clk->opaque = env;
ppc_dcr_init(env, NULL, NULL);
/* Register qemu callbacks */
- qemu_register_reset(&cpu_ppc_reset, env);
+ qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
return env;
}
#if 0
env->osi_call = vga_osi_call;
#endif
- qemu_register_reset(&cpu_ppc_reset, env);
+ qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
envs[i] = env;
}
/* Set time-base frequency to 16.6 Mhz */
cpu_ppc_tb_init(env, 16600000UL);
env->osi_call = vga_osi_call;
- qemu_register_reset(&cpu_ppc_reset, env);
+ qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
envs[i] = env;
}
/* Set time-base frequency to 100 Mhz */
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
}
- qemu_register_reset(&cpu_ppc_reset, env);
+ qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
envs[i] = env;
}
#endif /* !defined(CONFIG_USER_ONLY) */
void ppc_store_msr (CPUPPCState *env, target_ulong value);
-void cpu_ppc_reset (void *opaque);
-
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
const ppc_def_t *cpu_ppc_find_by_name (const char *name);
TARGET_FMT_lx "\n", RA, msr);
}
-void cpu_ppc_reset (void *opaque)
+void cpu_reset(CPUPPCState *env)
{
- CPUPPCState *env = opaque;
target_ulong msr;
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
env->cpu_model_str = cpu_model;
cpu_ppc_register_internal(env, def);
#if defined(CONFIG_USER_ONLY)
- cpu_ppc_reset(env);
+ cpu_reset(env);
#endif
qemu_init_vcpu(env);