arm64: tegra: Add blank lines for better readability
authorThierry Reding <treding@nvidia.com>
Wed, 26 Jul 2023 18:25:32 +0000 (20:25 +0200)
committerThierry Reding <treding@nvidia.com>
Thu, 27 Jul 2023 14:48:25 +0000 (16:48 +0200)
Add a few blank lines to visually separate blocks in the Jetson AGX Orin
device tree.

Signed-off-by: Thierry Reding <treding@nvidia.com>
arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts

index 722fa21..4413a9b 100644 (file)
@@ -90,6 +90,7 @@
                                        mode = "otg";
                                        usb-role-switch;
                                        status = "okay";
+
                                        port {
                                                hs_typec_p1: endpoint {
                                                        remote-endpoint = <&hs_ucsi_ccg_p1>;
                                usb2-1 {
                                        mode = "host";
                                        status = "okay";
+
                                        port {
                                                hs_typec_p0: endpoint {
                                                        remote-endpoint = <&hs_ucsi_ccg_p0>;
                                usb3-0 {
                                        nvidia,usb2-companion = <1>;
                                        status = "okay";
+
                                        port {
                                                ss_typec_p0: endpoint {
                                                        remote-endpoint = <&ss_ucsi_ccg_p0>;
                                usb3-1 {
                                        nvidia,usb2-companion = <0>;
                                        status = "okay";
+
                                        port {
                                                ss_typec_p1: endpoint {
                                                        remote-endpoint = <&ss_ucsi_ccg_p1>;
 
                                                port@0 {
                                                        reg = <0>;
+
                                                        hs_ucsi_ccg_p0: endpoint {
                                                                remote-endpoint = <&hs_typec_p0>;
                                                        };
 
                                                port@1 {
                                                        reg = <1>;
+
                                                        ss_ucsi_ccg_p0: endpoint {
                                                                remote-endpoint = <&ss_typec_p0>;
                                                        };
 
                                                port@0 {
                                                        reg = <0>;
+
                                                        hs_ucsi_ccg_p1: endpoint {
                                                                remote-endpoint = <&hs_typec_p1>;
                                                        };
 
                                                port@1 {
                                                        reg = <1>;
+
                                                        ss_ucsi_ccg_p1: endpoint {
                                                                remote-endpoint = <&ss_typec_p1>;
                                                        };