media: add codec support for tl1 [1/1]

PD#172587

Problem:
Bringup codec for TL1.

Solution:
Add codec iomap device tree node for TL1.
Add canvas device tree node for TL1.

Verify:
Verified on PXP/PTM.

Change-Id: I8b9a6645f1f9fd7d4aa9cae6166895e61ddc3e36
Signed-off-by: pengcheng chen <pengcheng.chen@amlogic.com>

diff --git a/arch/arm/boot/dts/amlogic/mesontl1.dtsi b/arch/arm/boot/dts/amlogic/mesontl1.dtsi
index 2a8c656..7a76d0f 100644 (file)
--- a/arch/arm/boot/dts/amlogic/mesontl1.dtsi
+++ b/arch/arm/boot/dts/amlogic/mesontl1.dtsi
@@ -884,6 +884,40 @@
                        "mailbox_2";
        };
 
+       canvas: canvas{
+               compatible = "amlogic, meson, canvas";
+               status = "okay";
+               reg = <0xff638000 0x2000>;
+       };
+
+       codec_io: codec_io {
+               compatible = "amlogic, codec_io";
+               status = "okay";
+               #address-cells=<1>;
+               #size-cells=<1>;
+               ranges;
+               io_cbus_base{
+                       reg = <0xffd00000 0x100000>;
+               };
+               io_dos_base{
+                       reg = <0xff620000 0x10000>;
+               };
+               io_hiubus_base{
+                       reg = <0xff63c000 0x2000>;
+               };
+               io_aobus_base{
+                       reg = <0xff800000 0x10000>;
+               };
+               io_vcbus_base{
+                       reg = <0xff900000 0x40000>;
+               };
+               io_dmc_base{
+                       reg = <0xff638000 0x2000>;
+               };
+               io_efuse_base{
+                       reg = <0xff630000 0x2000>;
+               };
+       };
 }; /* end of / */
 
 &pinctrl_aobus {

diff --git a/drivers/amlogic/media/common/arch/registers/register_ops_m8.c b/drivers/amlogic/media/common/arch/registers/register_ops_m8.c
index 8e81c09..2d51a44 100644 (file)
--- a/drivers/amlogic/media/common/arch/registers/register_ops_m8.c
+++ b/drivers/amlogic/media/common/arch/registers/register_ops_m8.c
@@ -31,6 +31,7 @@
        MESON_CPU_MAJOR_ID_AXG, \
        MESON_CPU_MAJOR_ID_G12A, \
        MESON_CPU_MAJOR_ID_G12B, \
+       MESON_CPU_MAJOR_ID_TL1, \
                        0}
 #define REGISTER_FOR_GXCPU {\
        MESON_CPU_MAJOR_ID_GXBB, \
@@ -42,6 +43,7 @@
        MESON_CPU_MAJOR_ID_AXG, \
        MESON_CPU_MAJOR_ID_G12A, \
        MESON_CPU_MAJOR_ID_G12B, \
+       MESON_CPU_MAJOR_ID_TL1, \
                        0}
 int codec_apb_read(unsigned int reg)
 {