pci: Add defines for normal and subtractive PCI bridges

Add following two new PCI class codes defines into pci_ids.h include file:

  PCI_CLASS_BRIDGE_PCI_NORMAL
  PCI_CLASS_BRIDGE_PCI_SUBTRACTIVE

And use these defines in all U-Boot code for describing PCI class codes for
normal and subtractive PCI bridges.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c
index 1e74158..e553da8 100644 (file)
--- a/board/armltd/vexpress64/pcie.c
+++ b/board/armltd/vexpress64/pcie.c
@@ -150,7 +150,7 @@ static void xr3pci_init(void)
        /* allow ECRC */
        writel(0x6006, XR3_CONFIG_BASE + XR3PCI_PEX_SPC2);
        /* setup the correct class code for the host bridge */
-       writel(PCI_CLASS_BRIDGE_PCI << 16, XR3_CONFIG_BASE + XR3PCI_BRIDGE_PCI_IDS);
+       writel(PCI_CLASS_BRIDGE_PCI_NORMAL << 8, XR3_CONFIG_BASE + XR3PCI_BRIDGE_PCI_IDS);
 
        /* reset phy and root complex */
        writel(JUNO_RESET_CTRL_PHY | JUNO_RESET_CTRL_RC,

diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 4f7e61e..b0fc9ca 100644 (file)
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -800,7 +800,7 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
         */
        reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION);
        reg &= ~0xffffff00;
-       reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
+       reg |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
        advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION);
 
        /* Enable generation and checking of ECRC on PCIe Root Port */

diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c
index 34a561e..4902923 100644 (file)
--- a/drivers/pci/pci-rcar-gen3.c
+++ b/drivers/pci/pci-rcar-gen3.c
@@ -289,7 +289,7 @@ static int rcar_gen3_pcie_hw_init(struct udevice *dev)
         * class to match. Hardware takes care of propagating the IDSETR
         * settings, so there is no need to bother with a quirk.
         */
-       writel(PCI_CLASS_BRIDGE_PCI << 16, priv->regs + IDSETR1);
+       writel(PCI_CLASS_BRIDGE_PCI_NORMAL << 8, priv->regs + IDSETR1);
 
        /*
         * Setup Secondary Bus Number & Subordinate Bus Number, even though

diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index f076693..d80f87e 100644 (file)
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -440,7 +440,7 @@ static int mvebu_pcie_probe(struct udevice *dev)
         */
        reg = readl(pcie->base + MVPCIE_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION);
        reg &= ~0xffffff00;
-       reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
+       reg |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
        writel(reg, pcie->base + MVPCIE_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION);
 
        /*

diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c
index fc05ee0..f8d66c0 100644 (file)
--- a/drivers/pci/pci_tegra.c
+++ b/drivers/pci/pci_tegra.c
@@ -325,8 +325,8 @@ static int pci_tegra_read_config(const struct udevice *bus, pci_dev_t bdf,
        /* fixup root port class */
        if (PCI_BUS(bdf) == 0) {
                if ((offset & ~3) == PCI_CLASS_REVISION) {
-                       value &= ~0x00ff0000;
-                       value |= PCI_CLASS_BRIDGE_PCI << 16;
+                       value &= ~0x00ffff00;
+                       value |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
                }
        }
 #endif

diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c
index 0490fd3..99891dc 100644 (file)
--- a/drivers/pci/pcie_dw_mvebu.c
+++ b/drivers/pci/pcie_dw_mvebu.c
@@ -539,9 +539,9 @@ static int pcie_dw_mvebu_probe(struct udevice *dev)
                                  PCIE_ATU_TYPE_MEM, pcie->mem.phys_start,
                                  pcie->mem.bus_start, pcie->mem.size);
 
-       /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
+       /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI_NORMAL */
        clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION,
-                       0xffff << 16, PCI_CLASS_BRIDGE_PCI << 16);
+                       0xffffff << 8, PCI_CLASS_BRIDGE_PCI_NORMAL << 8);
 
        pcie_dw_set_host_bars(pcie->ctrl_base);
 

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index cc6efdd..f5ba349 100644 (file)
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -532,7 +532,7 @@ static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
 
        fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val);
        val &= 0xff;
-       val |= PCI_CLASS_BRIDGE_PCI << 16;
+       val |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
        fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);
 
        if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)

diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index 756166f..2cec390 100644 (file)
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -300,9 +300,9 @@ static int imx_pcie_regions_setup(struct imx_pcie_priv *priv)
        setbits_le32(priv->dbi_base + PCI_COMMAND,
                     PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 
-       /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
+       /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI_NORMAL */
        setbits_le32(priv->dbi_base + PCI_CLASS_REVISION,
-                    PCI_CLASS_BRIDGE_PCI << 16);
+                    PCI_CLASS_BRIDGE_PCI_NORMAL << 8);
 
        /* Region #0 is used for Outbound CFG space access. */
        writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);

diff --git a/drivers/pci/pcie_iproc.c b/drivers/pci/pcie_iproc.c
index 85dfab5..d6d3a9e 100644 (file)
--- a/drivers/pci/pcie_iproc.c
+++ b/drivers/pci/pcie_iproc.c
@@ -1123,7 +1123,7 @@ static int iproc_pcie_check_link(struct iproc_pcie *pcie)
                                    PCI_BRIDGE_CTRL_REG_OFFSET,
                                    4, &class);
        class &= ~PCI_BRIDGE_CTRL_REG_CLASS_MASK;
-       class |= (PCI_CLASS_BRIDGE_PCI << 8);
+       class |= PCI_CLASS_BRIDGE_PCI_NORMAL;
        iproc_pci_raw_config_write32(pcie, 0,
                                     PCI_BRIDGE_CTRL_REG_OFFSET,
                                     4, class);

diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c
index 67039d2..72b4139 100644 (file)
--- a/drivers/pci/pcie_rockchip.c
+++ b/drivers/pci/pcie_rockchip.c
@@ -351,7 +351,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
 
        /* Initialize Root Complex registers. */
        writel(PCIE_LM_VENDOR_ROCKCHIP, priv->apb_base + PCIE_LM_VENDOR_ID);
-       writel(PCI_CLASS_BRIDGE_PCI << 16,
+       writel(PCI_CLASS_BRIDGE_PCI_NORMAL << 8,
               priv->apb_base + PCIE_RC_BASE + PCI_CLASS_REVISION);
        writel(PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS,
               priv->apb_base + PCIE_LM_RCBAR);

diff --git a/include/pci_ids.h b/include/pci_ids.h
index 3c5434c..88b0a64 100644 (file)
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -55,6 +55,8 @@
 #define PCI_CLASS_BRIDGE_EISA          0x0602
 #define PCI_CLASS_BRIDGE_MC            0x0603
 #define PCI_CLASS_BRIDGE_PCI           0x0604
+#define PCI_CLASS_BRIDGE_PCI_NORMAL            0x060400
+#define PCI_CLASS_BRIDGE_PCI_SUBTRACTIVE       0x060401
 #define PCI_CLASS_BRIDGE_PCMCIA                0x0605
 #define PCI_CLASS_BRIDGE_NUBUS         0x0606
 #define PCI_CLASS_BRIDGE_CARDBUS       0x0607