[PowerPC] Automatically generate store-constant.ll . NFC

diff --git a/llvm/test/CodeGen/PowerPC/store-constant.ll b/llvm/test/CodeGen/PowerPC/store-constant.ll
index bc84702..7e562eb 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/store-constant.ll
+++ b/llvm/test/CodeGen/PowerPC/store-constant.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s
 
 @CVal = external local_unnamed_addr global i8, align 1
@@ -13,6 +14,14 @@
 %struct.S = type { i64, i8, i16, i32 }
 
 define void @foo(%struct.S* %p) {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 4, 0
+; CHECK-NEXT:    stb 4, 8(3)
+; CHECK-NEXT:    std 4, 0(3)
+; CHECK-NEXT:    sth 4, 10(3)
+; CHECK-NEXT:    stw 4, 12(3)
+; CHECK-NEXT:    blr
   %l4 = bitcast %struct.S* %p to i64*
   store i64 0, i64* %l4, align 8
   %c = getelementptr %struct.S, %struct.S* %p, i64 0, i32 1
@@ -23,15 +32,17 @@ define void @foo(%struct.S* %p) {
   store i32 0, i32* %i, align 4
   ret void
 
-; CHECK-LABEL: @foo
-; CHECK:       li 4, 0
-; CHECK:       stb 4, 8(3)
-; CHECK:       std 4, 0(3)
-; CHECK:       sth 4, 10(3)
-; CHECK:       stw 4, 12(3)
 }
 
 define void @bar(%struct.S* %p) {
+; CHECK-LABEL: bar:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 4, 2
+; CHECK-NEXT:    stw 4, 12(3)
+; CHECK-NEXT:    sth 4, 10(3)
+; CHECK-NEXT:    std 4, 0(3)
+; CHECK-NEXT:    stb 4, 8(3)
+; CHECK-NEXT:    blr
   %i = getelementptr %struct.S, %struct.S* %p, i64 0, i32 3
   store i32 2, i32* %i, align 4
   %s = getelementptr %struct.S, %struct.S* %p, i64 0, i32 2
@@ -42,103 +53,171 @@ define void @bar(%struct.S* %p) {
   store i64 2, i64* %l4, align 8
   ret void
 
-; CHECK-LABEL: @bar
-; CHECK:       li 4, 2
-; CHECK-DAG:       stw 4, 12(3)
-; CHECK-DAG:       sth 4, 10(3)
-; CHECK-DAG:       std 4, 0(3)
-; CHECK-DAG:       stb 4, 8(3)
 }
 
 ; Function Attrs: norecurse nounwind
 define void @setSmallNeg() {
+; CHECK-LABEL: setSmallNeg:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:    addis 4, 2, .LC1@toc@ha
+; CHECK-NEXT:    addis 5, 2, .LC2@toc@ha
+; CHECK-NEXT:    addis 6, 2, .LC3@toc@ha
+; CHECK-NEXT:    li 7, -7
+; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:    ld 4, .LC1@toc@l(4)
+; CHECK-NEXT:    ld 5, .LC2@toc@l(5)
+; CHECK-NEXT:    ld 6, .LC3@toc@l(6)
+; CHECK-NEXT:    stb 7, 0(3)
+; CHECK-NEXT:    sth 7, 0(4)
+; CHECK-NEXT:    std 7, 0(6)
+; CHECK-NEXT:    stw 7, 0(5)
+; CHECK-NEXT:    blr
 entry:
   store i8 -7, i8* @CVal, align 1
   store i16 -7, i16* @SVal, align 2
   store i32 -7, i32* @IVal, align 4
   store i64 -7, i64* @LVal, align 8
   ret void
-; CHECK-LABEL: setSmallNeg
-; CHECK: li 7, -7
-; CHECK-DAG: stb 7,
-; CHECK-DAG: sth 7,
-; CHECK-DAG: stw 7,
-; CHECK-DAG: std 7,
 }
 
 ; Function Attrs: norecurse nounwind
 define void @setSmallPos() {
+; CHECK-LABEL: setSmallPos:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:    addis 4, 2, .LC1@toc@ha
+; CHECK-NEXT:    addis 5, 2, .LC2@toc@ha
+; CHECK-NEXT:    addis 6, 2, .LC3@toc@ha
+; CHECK-NEXT:    li 7, 8
+; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:    ld 4, .LC1@toc@l(4)
+; CHECK-NEXT:    ld 5, .LC2@toc@l(5)
+; CHECK-NEXT:    ld 6, .LC3@toc@l(6)
+; CHECK-NEXT:    stb 7, 0(3)
+; CHECK-NEXT:    sth 7, 0(4)
+; CHECK-NEXT:    std 7, 0(6)
+; CHECK-NEXT:    stw 7, 0(5)
+; CHECK-NEXT:    blr
 entry:
   store i8 8, i8* @CVal, align 1
   store i16 8, i16* @SVal, align 2
   store i32 8, i32* @IVal, align 4
   store i64 8, i64* @LVal, align 8
   ret void
-; CHECK-LABEL: setSmallPos
-; CHECK: li 7, 8
-; CHECK-DAG: stb 7,
-; CHECK-DAG: sth 7,
-; CHECK-DAG: stw 7,
-; CHECK-DAG: std 7,
 }
 
 ; Function Attrs: norecurse nounwind
 define void @setMaxNeg() {
+; CHECK-LABEL: setMaxNeg:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, .LC1@toc@ha
+; CHECK-NEXT:    addis 4, 2, .LC2@toc@ha
+; CHECK-NEXT:    addis 5, 2, .LC3@toc@ha
+; CHECK-NEXT:    li 6, -32768
+; CHECK-NEXT:    ld 3, .LC1@toc@l(3)
+; CHECK-NEXT:    ld 4, .LC2@toc@l(4)
+; CHECK-NEXT:    ld 5, .LC3@toc@l(5)
+; CHECK-NEXT:    sth 6, 0(3)
+; CHECK-NEXT:    stw 6, 0(4)
+; CHECK-NEXT:    std 6, 0(5)
+; CHECK-NEXT:    blr
 entry:
   store i16 -32768, i16* @SVal, align 2
   store i32 -32768, i32* @IVal, align 4
   store i64 -32768, i64* @LVal, align 8
   ret void
-; CHECK-LABEL: setMaxNeg
-; CHECK: li 6, -32768
-; CHECK-DAG: sth 6,
-; CHECK-DAG: stw 6,
-; CHECK-DAG: std 6,
 }
 
 ; Function Attrs: norecurse nounwind
 define void @setMaxPos() {
+; CHECK-LABEL: setMaxPos:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, .LC1@toc@ha
+; CHECK-NEXT:    addis 4, 2, .LC2@toc@ha
+; CHECK-NEXT:    addis 5, 2, .LC3@toc@ha
+; CHECK-NEXT:    li 6, 32767
+; CHECK-NEXT:    ld 3, .LC1@toc@l(3)
+; CHECK-NEXT:    ld 4, .LC2@toc@l(4)
+; CHECK-NEXT:    ld 5, .LC3@toc@l(5)
+; CHECK-NEXT:    sth 6, 0(3)
+; CHECK-NEXT:    stw 6, 0(4)
+; CHECK-NEXT:    std 6, 0(5)
+; CHECK-NEXT:    blr
 entry:
   store i16 32767, i16* @SVal, align 2
   store i32 32767, i32* @IVal, align 4
   store i64 32767, i64* @LVal, align 8
   ret void
-; CHECK-LABEL: setMaxPos
-; CHECK: li 6, 32767
-; CHECK-DAG: sth 6,
-; CHECK-DAG: stw 6,
-; CHECK-DAG: std 6,
 }
 
 ; Function Attrs: norecurse nounwind
 define void @setExcessiveNeg() {
+; CHECK-LABEL: setExcessiveNeg:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, .LC2@toc@ha
+; CHECK-NEXT:    addis 4, 2, .LC3@toc@ha
+; CHECK-NEXT:    lis 5, -1
+; CHECK-NEXT:    ld 3, .LC2@toc@l(3)
+; CHECK-NEXT:    ld 4, .LC3@toc@l(4)
+; CHECK-NEXT:    ori 5, 5, 32767
+; CHECK-NEXT:    stw 5, 0(3)
+; CHECK-NEXT:    std 5, 0(4)
+; CHECK-NEXT:    blr
 entry:
   store i32 -32769, i32* @IVal, align 4
   store i64 -32769, i64* @LVal, align 8
   ret void
-; CHECK-LABEL: setExcessiveNeg
-; CHECK: lis 5, -1
-; CHECK: ori 5, 5, 32767
-; CHECK-DAG: stw 5,
-; CHECK-DAG: std 5,
 }
 
 ; Function Attrs: norecurse nounwind
 define void @setExcessivePos() {
+; CHECK-LABEL: setExcessivePos:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, .LC4@toc@ha
+; CHECK-NEXT:    addis 4, 2, .LC2@toc@ha
+; CHECK-NEXT:    addis 5, 2, .LC3@toc@ha
+; CHECK-NEXT:    li 6, 0
+; CHECK-NEXT:    ld 3, .LC4@toc@l(3)
+; CHECK-NEXT:    ld 4, .LC2@toc@l(4)
+; CHECK-NEXT:    ld 5, .LC3@toc@l(5)
+; CHECK-NEXT:    ori 6, 6, 32768
+; CHECK-NEXT:    sth 6, 0(3)
+; CHECK-NEXT:    stw 6, 0(4)
+; CHECK-NEXT:    std 6, 0(5)
+; CHECK-NEXT:    blr
 entry:
   store i16 -32768, i16* @USVal, align 2
   store i32 32768, i32* @IVal, align 4
   store i64 32768, i64* @LVal, align 8
   ret void
-; CHECK-LABEL: setExcessivePos
-; CHECK: li 6, 0
-; CHECK: ori 6, 6, 32768
-; CHECK-DAG: sth 6,
-; CHECK-DAG: stw 6,
-; CHECK-DAG: std 6,
 }
 
 define void @SetArr(i32 signext %Len) {
+; CHECK-LABEL: SetArr:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpwi 3, 1
+; CHECK-NEXT:    bltlr 0
+; CHECK-NEXT:  # %bb.1: # %for.body.lr.ph
+; CHECK-NEXT:    addis 4, 2, .LC5@toc@ha
+; CHECK-NEXT:    addis 5, 2, .LC6@toc@ha
+; CHECK-NEXT:    clrldi 6, 3, 32
+; CHECK-NEXT:    ld 4, .LC5@toc@l(4)
+; CHECK-NEXT:    ld 5, .LC6@toc@l(5)
+; CHECK-NEXT:    ld 4, 0(4)
+; CHECK-NEXT:    ld 5, 0(5)
+; CHECK-NEXT:    mtctr 6
+; CHECK-NEXT:    addi 3, 4, -8
+; CHECK-NEXT:    addi 4, 5, -4
+; CHECK-NEXT:    li 5, -7
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB8_2: # %for.body
+; CHECK-NEXT:    #
+; CHECK-NEXT:    stdu 5, 8(3)
+; CHECK-NEXT:    stwu 5, 4(4)
+; CHECK-NEXT:    bdnz .LBB8_2
+; CHECK-NEXT:  # %bb.3: # %for.cond.cleanup
+; CHECK-NEXT:    blr
 entry:
   %cmp7 = icmp sgt i32 %Len, 0
   br i1 %cmp7, label %for.body.lr.ph, label %for.cond.cleanup
@@ -161,31 +240,39 @@ for.body:                                         ; preds = %for.body, %for.body
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count
   br i1 %exitcond, label %for.cond.cleanup, label %for.body
-; CHECK-LABEL: SetArr
-; CHECK: li 5, -7
-; CHECK: stdu 5, 8(3)
-; CHECK: stwu 5, 4(4)
 }
 
 define void @setSameValDiffSizeCI() {
+; CHECK-LABEL: setSameValDiffSizeCI:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, .LC2@toc@ha
+; CHECK-NEXT:    addis 4, 2, .LC0@toc@ha
+; CHECK-NEXT:    li 5, 255
+; CHECK-NEXT:    ld 3, .LC2@toc@l(3)
+; CHECK-NEXT:    ld 4, .LC0@toc@l(4)
+; CHECK-NEXT:    stw 5, 0(3)
+; CHECK-NEXT:    stb 5, 0(4)
+; CHECK-NEXT:    blr
 entry:
   store i32 255, i32* @IVal, align 4
   store i8 -1, i8* @CVal, align 1
   ret void
-; CHECK-LABEL: setSameValDiffSizeCI
-; CHECK: li 5, 255
-; CHECK-DAG: stb 5,
-; CHECK-DAG: stw 5,
 }
 
 define void @setSameValDiffSizeSI() {
+; CHECK-LABEL: setSameValDiffSizeSI:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, .LC2@toc@ha
+; CHECK-NEXT:    addis 4, 2, .LC1@toc@ha
+; CHECK-NEXT:    li 5, 0
+; CHECK-NEXT:    ld 3, .LC2@toc@l(3)
+; CHECK-NEXT:    ld 4, .LC1@toc@l(4)
+; CHECK-NEXT:    ori 5, 5, 65535
+; CHECK-NEXT:    stw 5, 0(3)
+; CHECK-NEXT:    sth 5, 0(4)
+; CHECK-NEXT:    blr
 entry:
   store i32 65535, i32* @IVal, align 4
   store i16 -1, i16* @SVal, align 2
   ret void
-; CHECK-LABEL: setSameValDiffSizeSI
-; CHECK: li 5, 0
-; CHECK: ori 5, 5, 65535
-; CHECK-DAG: sth 5,
-; CHECK-DAG: stw 5,
 }