radv,radeonsi: Disable compression on interop depth images
authorBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Thu, 13 Aug 2020 22:58:06 +0000 (00:58 +0200)
committerMarge Bot <eric+marge@anholt.net>
Sun, 20 Sep 2020 23:51:58 +0000 (23:51 +0000)
If we want to use HTILE correctly we need to communicate extra stuff
like clear colors. (Unlike DCC there is no HTILE FCE)

CC: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6617>

src/amd/vulkan/radv_image.c
src/gallium/drivers/radeonsi/si_texture.c

index 43ccec3..cc0ae66 100644 (file)
@@ -268,6 +268,7 @@ radv_use_htile_for_image(const struct radv_device *device,
                          const struct radv_image *image)
 {
        return image->info.levels == 1 &&
+              !image->shareable &&
               ((image->info.width * image->info.height >= 8 * 8) ||
                (device->instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS));
 }
index 448e749..b66f8eb 100644 (file)
@@ -237,7 +237,8 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac
    if (!is_flushed_depth && is_depth) {
       flags |= RADEON_SURF_ZBUFFER;
 
-      if (sscreen->debug_flags & DBG(NO_HYPERZ)) {
+      if ((sscreen->debug_flags & DBG(NO_HYPERZ)) ||
+          (ptex->bind & PIPE_BIND_SHARED) || is_imported) {
          flags |= RADEON_SURF_NO_HTILE;
       } else if (tc_compatible_htile &&
                  (sscreen->info.chip_class >= GFX9 || array_mode == RADEON_SURF_MODE_2D)) {