bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
const ReturnInst &RI = cast<ReturnInst>(U);
const Value *Ret = RI.getReturnValue();
+ if (Ret && DL->getTypeStoreSize(Ret->getType()) == 0)
+ Ret = nullptr;
// The target may mess up with the insertion point, but
// this is not important as a return is the last instruction
// of the block anyway.
: MachineMemOperand::MONone;
Flags |= MachineMemOperand::MOLoad;
+ if (DL->getTypeStoreSize(LI.getType()) == 0)
+ return true;
+
unsigned Res = getOrCreateVReg(LI);
unsigned Addr = getOrCreateVReg(*LI.getPointerOperand());
: MachineMemOperand::MONone;
Flags |= MachineMemOperand::MOStore;
+ if (DL->getTypeStoreSize(SI.getValueOperand()->getType()) == 0)
+ return true;
+
unsigned Val = getOrCreateVReg(*SI.getValueOperand());
unsigned Addr = getOrCreateVReg(*SI.getPointerOperand());
// Lower the actual args into this basic block.
SmallVector<unsigned, 8> VRegArgs;
- for (const Argument &Arg: F.args())
+ for (const Argument &Arg: F.args()) {
+ if (DL->getTypeStoreSize(Arg.getType()) == 0)
+ continue; // Don't handle zero sized types.
VRegArgs.push_back(getOrCreateVReg(Arg));
+ }
if (!CLI->lowerFormalArguments(EntryBuilder, F, VRegArgs)) {
OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
MF->getFunction()->getSubprogram(),
SmallVector<ArgInfo, 8> SplitArgs;
unsigned i = 0;
for (auto &Arg : F.args()) {
+ if (DL.getTypeStoreSize(Arg.getType()) == 0)
+ continue;
ArgInfo OrigArg{VRegs[i], Arg.getType()};
setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F);
bool Split = false;
}
declare i64 @llvm.aarch64.ldxr.p0i32(i32*) nounwind
+
+%zerosize_type = type {}
+
+define %zerosize_type @test_empty_load_store(%zerosize_type *%ptr, %zerosize_type %in) noinline optnone {
+; CHECK-LABEL: name: test_empty_load_store
+; CHECK-NOT: G_STORE
+; CHECK-NOT: G_LOAD
+; CHECK: RET_ReallyLR
+entry:
+ store %zerosize_type undef, %zerosize_type* undef, align 4
+ %val = load %zerosize_type, %zerosize_type* %ptr, align 4
+ ret %zerosize_type %in
+}