// by a memory dependency.
unsigned CriticalMemDep;
+ // True if this instruction has been optimized at register renaming stage.
+ bool IsEliminated;
+
public:
Instruction(const InstrDesc &D)
: InstructionBase(D), Stage(IS_INVALID), CyclesLeft(UNKNOWN_CYCLES),
- RCUTokenID(0), CriticalResourceMask(0), CriticalMemDep(0) {}
+ RCUTokenID(0), CriticalResourceMask(0), CriticalMemDep(0),
+ IsEliminated(false) {}
unsigned getRCUTokenID() const { return RCUTokenID; }
int getCyclesLeft() const { return CyclesLeft; }
bool isExecuting() const { return Stage == IS_EXECUTING; }
bool isExecuted() const { return Stage == IS_EXECUTED; }
bool isRetired() const { return Stage == IS_RETIRED; }
-
- bool isEliminated() const {
- return isReady() && getDefs().size() &&
- all_of(getDefs(),
- [](const WriteState &W) { return W.isEliminated(); });
- }
+ bool isEliminated() const { return IsEliminated; }
// Forces a transition from state IS_DISPATCHED to state IS_EXECUTED.
void forceExecuted();
+ void setEliminated() { IsEliminated = true; }
void retire() {
assert(isExecuted() && "Instruction is in an invalid state!");
AvailableEntries = 0;
// Check if this is an optimizable reg-reg move.
- bool IsEliminated = false;
if (IS.isOptimizableMove()) {
assert(IS.getDefs().size() == 1 && "Expected a single input!");
assert(IS.getUses().size() == 1 && "Expected a single output!");
- IsEliminated = PRF.tryEliminateMove(IS.getDefs()[0], IS.getUses()[0]);
+ if (PRF.tryEliminateMove(IS.getDefs()[0], IS.getUses()[0]))
+ IS.setEliminated();
}
if (IS.isMemOp())
//
// We also don't update data dependencies for instructions that have been
// eliminated at register renaming stage.
- if (!IsEliminated) {
+ if (!IS.isEliminated()) {
for (ReadState &RS : IS.getUses())
PRF.addRegisterRead(RS, STI);
}