[RISCV] Add missing tests for vector type for second operand of vmsgt and vmsgtu...

Refactor to use new multiclass instead of individual patterns.

We already supported this due to SEW=64 on RV32, but we didn't have
test cases for all the types we supported.

Part of D100925

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 43c3861..af589d2 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -3949,50 +3949,8 @@ defm : VPatBinaryM_VX_VI<"int_riscv_vmsgtu", "PseudoVMSGTU", AllIntegerVectors>;
 defm : VPatBinaryM_VX_VI<"int_riscv_vmsgt", "PseudoVMSGT", AllIntegerVectors>;
 
 // Match vmsgt with 2 vector operands to vmslt with the operands swapped.
-// Occurs when legalizing vmsgt(u).vx intrinsics for i64 on RV32 since we need
-// to use a more complex splat sequence. Add the pattern for all VTs for
-// consistency.
-foreach vti = AllIntegerVectors in {
-  def : Pat<(vti.Mask (int_riscv_vmsgt (vti.Vector vti.RegClass:$rs2),
-                                       (vti.Vector vti.RegClass:$rs1),
-                                       VLOpFrag)),
-            (!cast<Instruction>("PseudoVMSLT_VV_"#vti.LMul.MX) vti.RegClass:$rs1,
-                                                               vti.RegClass:$rs2,
-                                                               GPR:$vl,
-                                                               vti.SEW)>;
-  def : Pat<(vti.Mask (int_riscv_vmsgt_mask (vti.Mask VR:$merge),
-                                            (vti.Vector vti.RegClass:$rs2),
-                                            (vti.Vector vti.RegClass:$rs1),
-                                            (vti.Mask V0),
-                                            VLOpFrag)),
-            (!cast<Instruction>("PseudoVMSLT_VV_"#vti.LMul.MX#"_MASK")
-                                                      VR:$merge,
-                                                      vti.RegClass:$rs1,
-                                                      vti.RegClass:$rs2,
-                                                      (vti.Mask V0),
-                                                      GPR:$vl,
-                                                      vti.SEW)>;
-
-  def : Pat<(vti.Mask (int_riscv_vmsgtu (vti.Vector vti.RegClass:$rs2),
-                                        (vti.Vector vti.RegClass:$rs1),
-                                        VLOpFrag)),
-            (!cast<Instruction>("PseudoVMSLTU_VV_"#vti.LMul.MX) vti.RegClass:$rs1,
-                                                                vti.RegClass:$rs2,
-                                                                GPR:$vl,
-                                                                vti.SEW)>;
-  def : Pat<(vti.Mask (int_riscv_vmsgtu_mask (vti.Mask VR:$merge),
-                                             (vti.Vector vti.RegClass:$rs2),
-                                             (vti.Vector vti.RegClass:$rs1),
-                                             (vti.Mask V0),
-                                             VLOpFrag)),
-            (!cast<Instruction>("PseudoVMSLTU_VV_"#vti.LMul.MX#"_MASK")
-                                                       VR:$merge,
-                                                       vti.RegClass:$rs1,
-                                                       vti.RegClass:$rs2,
-                                                       (vti.Mask V0),
-                                                       GPR:$vl,
-                                                       vti.SEW)>;
-}
+defm : VPatBinarySwappedM_VV<"int_riscv_vmsgtu", "PseudoVMSLTU", AllIntegerVectors>;
+defm : VPatBinarySwappedM_VV<"int_riscv_vmsgt", "PseudoVMSLT", AllIntegerVectors>;
 
 // Match vmslt(u).vx intrinsics to vmsle(u).vi if the scalar is -15 to 16. This
 // avoids the user needing to know that there is no vmslt(u).vi instruction.

diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
index 3af3410..504b44e 100644 (file)
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
@@ -1,6 +1,942 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
 ; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8(
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i8> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8(
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i8> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8(
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i8> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8(
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i8> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v10, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v10, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v12, v10, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8(
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i8> %3,
+    <vscale x 16 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsgt_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v12, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,m4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v12, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v16, v12, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8(
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i8> %3,
+    <vscale x 32 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16(
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i16> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16(
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i16> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16(
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i16> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v10, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v10, v8
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v12, v10, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16(
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i16> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v12, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v12, v8
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v16, v12, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16(
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i16> %3,
+    <vscale x 16 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32(
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i32> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32(
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i32> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v10, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v10, v8
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v12, v10, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32(
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i32> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v12, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v12, v8
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v16, v12, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32(
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i32> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vv_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64(
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i64> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vv_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v10, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v10, v8
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v12, v10, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64(
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i64> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vv_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v12, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e64,m4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v12, v8
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v16, v12, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64(
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i64> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
 declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8(
   <vscale x 1 x i8>,
   i8,

diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
index fcbb58f..e03678a 100644 (file)
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
@@ -1,6 +1,942 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
 ; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8(
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i8> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8(
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i8> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8(
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i8> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8(
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i8> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v10, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v10, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v12, v10, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8(
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i8> %3,
+    <vscale x 16 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsgt_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v12, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,m4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v12, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v16, v12, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8(
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i8> %3,
+    <vscale x 32 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16(
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i16> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16(
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i16> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16(
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i16> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v10, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v10, v8
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v12, v10, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16(
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i16> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v12, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v12, v8
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v16, v12, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16(
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i16> %3,
+    <vscale x 16 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32(
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i32> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32(
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i32> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v10, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v10, v8
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v12, v10, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32(
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i32> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v12, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v12, v8
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v16, v12, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32(
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i32> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vv_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64(
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i64> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vv_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v10, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v10, v8
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v12, v10, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64(
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i64> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vv_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_vv_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v12, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e64,m4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v12, v8
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,tu,mu
+; CHECK-NEXT:    vmslt.vv v25, v16, v12, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64(
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i64> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
 declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8(
   <vscale x 1 x i8>,
   i8,

diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
index 4404f00..839722c 100644 (file)
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
@@ -1,6 +1,942 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
 ; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8(
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i8> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8(
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i8> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8(
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i8> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8(
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i8> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v10, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v10, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v12, v10, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8(
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i8> %3,
+    <vscale x 16 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsgtu_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v12, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v12, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v16, v12, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8(
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i8> %3,
+    <vscale x 32 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16(
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i16> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16(
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i16> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16(
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i16> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v10, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v10, v8
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v12, v10, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16(
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i16> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v12, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v12, v8
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v16, v12, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16(
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i16> %3,
+    <vscale x 16 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32(
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i32> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32(
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i32> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v10, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v10, v8
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v12, v10, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32(
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i32> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v12, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v12, v8
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v16, v12, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32(
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i32> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vv_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64(
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i64> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vv_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v10, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v10, v8
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v12, v10, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64(
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i64> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vv_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v12, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e64,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v12, v8
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v16, v12, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64(
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i64> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
 declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8(
   <vscale x 1 x i8>,
   i8,

diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
index ecb29a1..fea3c22 100644 (file)
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
@@ -1,6 +1,942 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
 ; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8(
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i8> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8(
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i8> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8(
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i8> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8(
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i8> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v10, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v10, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v12, v10, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8(
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i8> %3,
+    <vscale x 16 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsgtu_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v12, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e8,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v12, v8
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v16, v12, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8(
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i8> %3,
+    <vscale x 32 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16(
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i16> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16(
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i16> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16(
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i16> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v10, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v10, v8
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v12, v10, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16(
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i16> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v12, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v12, v8
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v16, v12, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16(
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i16> %3,
+    <vscale x 16 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32(
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i32> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32(
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i32> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v10, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v10, v8
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v12, v10, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32(
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i32> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v12, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v12, v8
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v16, v12, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32(
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i32> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vv_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v9, v8
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v10, v9, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64(
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i64> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vv_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v10, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v10, v8
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v12, v10, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64(
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i64> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vv_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_vv_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v12, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v25, v0
+; CHECK-NEXT:    vsetvli a1, a0, e64,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v12, v8
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,tu,mu
+; CHECK-NEXT:    vmsltu.vv v25, v16, v12, v0.t
+; CHECK-NEXT:    vmv1r.v v0, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64(
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i64> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
 declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8(
   <vscale x 1 x i8>,
   i8,