* PPC405EP: Add support for board configuration of CPC0_PCI register

  This is needed to be able to configure PerWE*/PCI_INT* pin as PerWE*
Patch by Tolunay Orkun, 07 Apr 2006

diff --git a/CHANGELOG b/CHANGELOG
index 87a8746..2a40ab3 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,10 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* PPC405EP: Add support for board configuration of CPC0_PCI register
+  This is needed to be able to configure PerWE*/PCI_INT* pin as PerWE*
+  Patch by Tolunay Orkun, 07 Apr 2006
+
 * PPC405EP: Add CFG_GPIO0_OR, CFG_GPIO0_ODR to setup GPIO completely.
   - Add configuration of Open Drain GPIO Output selection
   - Add configuration of initial value of GPIO output pins

diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 3f29314..3fe13da 100644 (file)
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -1697,7 +1697,8 @@ ppc405ep_init:
        mtdcr   ebccfgd,r3
 #endif
 
-       addi    r3,0,CPC0_PCI_HOST_CFG_EN
+#ifndef CFG_CPC0_PCI
+       li      r3,CPC0_PCI_HOST_CFG_EN
 #ifdef CONFIG_BUBINGA
        /*
        !-----------------------------------------------------------------------
@@ -1712,6 +1713,9 @@ ppc405ep_init:
        beq     ..pci_cfg_set             /* if not set, then bypass reg write*/
 #endif
        ori     r3,r3,CPC0_PCI_ARBIT_EN
+#else /* CFG_CPC0_PCI */
+       li      r3,CFG_CPC0_PCI
+#endif /* CFG_CPC0_PCI */
 ..pci_cfg_set:
        mtdcr   CPC0_PCI, r3             /* Enable internal arbiter*/