projects
/
platform
/
kernel
/
linux-starfive.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
16038eb
)
PCI: mvebu: Update comment for PCI_EXP_LNKCAP register on emulated bridge
author
Pali Rohár
<pali@kernel.org>
Tue, 4 Jan 2022 15:35:27 +0000
(16:35 +0100)
committer
Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com>
Thu, 3 Feb 2022 10:54:06 +0000
(10:54 +0000)
Reason for clearing this bit is because mvebu hw returns incorrectly this bit set to 1.
Link:
https://lore.kernel.org/r/20220104153529.31647-10-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
drivers/pci/controller/pci-mvebu.c
patch
|
blob
|
history
diff --git
a/drivers/pci/controller/pci-mvebu.c
b/drivers/pci/controller/pci-mvebu.c
index
1a03fb3
..
216da12
100644
(file)
--- a/
drivers/pci/controller/pci-mvebu.c
+++ b/
drivers/pci/controller/pci-mvebu.c
@@
-546,8
+546,8
@@
mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
case PCI_EXP_LNKCAP:
/*
- * PCIe requires th
e clock power management capability to be
- *
hard-wired to zero for downstream ports
+ * PCIe requires th
at the Clock Power Management capability bit
+ *
is hard-wired to zero for downstream ports but HW returns 1.
*/
*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) &
~PCI_EXP_LNKCAP_CLKPM;