}
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
ulong top_addr;
*/
#define USABLE_RAM_SIZE 0x80000000ULL
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
unsigned long top = CFG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE);
return 0;
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
return 0;
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
phys_size_t size;
phys_addr_t reg;
};
struct mm_region *mem_map = sunxi_mem_map;
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
/* Some devices (like the EMAC) have a 32-bit DMA limit. */
if (gd->ram_top > (1ULL << 32))
* This function is called before dram_init_banksize(), so we can't simply
* return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
ulong ram_top;
}
#endif /* CONFIG_SPL_BUILD */
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
return CFG_SYS_SDRAM_BASE + (256 * 1024 * 1024);
}
return UBOOT_RAM_SIZE_MAX;
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
if (IS_ENABLED(CONFIG_RAM_OCTEON)) {
/* Map a maximum of 256MiB - return not size but address */
return fdtdec_setup_memory_banksize();
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
/*
* Ensure that we run from first 4GB so that all
return fdtdec_setup_memory_banksize();
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
#ifdef CONFIG_64BIT
/*
return fdtdec_setup_memory_banksize();
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
/*
* Ensure that we run from first 4GB so that all
return fdtdec_setup_memory_banksize();
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
/*
* Ensure that we run from first 4GB so that all
#include <asm/arch/pei_data.h>
#include <asm/arch/pm.h>
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
return mrc_common_board_get_usable_ram_top(total_size);
}
* address, and how far U-Boot is moved by relocation are set in the global
* data structure.
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
uintptr_t dest_addr = 0;
int i;
* the relocation address, and how far U-Boot is moved by relocation are
* set in the global data structure.
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
struct efi_mem_desc *desc, *end;
struct efi_entry_memmap *map;
DECLARE_GLOBAL_DATA_PTR;
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
return (ulong)efi_get_ram_base() + gd->ram_size;
}
#define CMOS_OFFSET_MRC_SEED_S3 156
#define CMOS_OFFSET_MRC_SEED_CHK 160
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
return mrc_common_board_get_usable_ram_top(total_size);
}
* the relocation address, and how far U-Boot is moved by relocation are
* set in the global data structure.
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
return qemu_get_low_memory_size();
}
* the relocation address, and how far U-Boot is moved by relocation are
* set in the global data structure.
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
return gd->ram_size;
}
* @total_size: The memory size that u-boot occupies
* Return: : The top available memory address lower than 4GB
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
struct sbl_memory_map_info *data;
int i;
* address, and how far U-Boot is moved by relocation are set in the global
* data structure.
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
struct sfi_table_simple *sb;
struct sfi_mem_entry *mentry;
void x86_enable_caches(void);
void x86_disable_caches(void);
int x86_init_cache(void);
-phys_size_t board_get_usable_ram_top(phys_size_t total_size);
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size);
int default_print_cpuinfo(void);
/* Set up a UART which can be used with printch(), printhex8(), etc. */
* the relocation address, and how far U-Boot is moved by relocation are
* set in the global data structure.
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
return fsp_get_usable_lowmem_top(gd->arch.hob_list);
}
return 0;
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
if (!ll_boot_init())
return gd->ram_size;
}
/* Limit RAM used by U-Boot to the DDR first bank End region */
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
return BCM_NS3_MEM_END;
}
return 0;
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
DECLARE_GLOBAL_DATA_PTR;
static u32 mx53_dram_size[2];
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
/*
* WARNING: We must override get_effective_memsize() function here
/*
* Prevent relocation from stomping on a firmware provided FDT blob.
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
if ((gd->ram_top - fw_dtb_pointer) > SZ_64M)
return gd->ram_top;
return 0;
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
#ifdef CONFIG_PHYS_64BIT
/* Limit RAM used by U-Boot to the DDR low region */
return 0;
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
#ifdef CONFIG_PHYS_64BIT
/* Limit RAM used by U-Boot to the DDR low region */
return 0;
}
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
#ifdef CONFIG_PHYS_64BIT
/* Limit RAM used by U-Boot to the DDR low region */
/*
* Avoid relocated U-Boot clash with Linux reserved-memory on 512 MB SoM
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
return 0x9C000000;
}
#endif
#if defined(CONFIG_LMB)
-phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
phys_size_t size;
phys_addr_t reg;
}
/* Get the top of usable RAM */
-__weak phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+__weak phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
#if defined(CFG_SYS_SDRAM_BASE) && CFG_SYS_SDRAM_BASE > 0
/*
* @total_size: monitor length in bytes (size of U-Boot code)
* Return: uppermost address for U-Boot relocation
*/
-phys_size_t board_get_usable_ram_top(phys_size_t total_size);
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size);
int board_early_init_f(void);