[MIRParser] Accept unsized generic instructions.

Since r276158, we require generic instructions to have a sized type.
G_BR doesn't; relax the restriction.

llvm-svn: 277006

diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 1ec3680..f49b524 100644 (file)
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -130,8 +130,7 @@ public:
   bool parseIRConstant(StringRef::iterator Loc, StringRef Source,
                        const Constant *&C);
   bool parseIRConstant(StringRef::iterator Loc, const Constant *&C);
-  bool parseLowLevelType(StringRef::iterator Loc, LLT &Ty,
-                         bool MustBeSized = true);
+  bool parseLowLevelType(StringRef::iterator Loc, LLT &Ty);
   bool parseTypedImmediateOperand(MachineOperand &Dest);
   bool parseFPImmediateOperand(MachineOperand &Dest);
   bool parseMBBReference(MachineBasicBlock *&MBB);
@@ -1039,11 +1038,8 @@ bool MIParser::parseIRConstant(StringRef::iterator Loc, const Constant *&C) {
   return false;
 }
 
-bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty,
-                                 bool MustBeSized) {
+bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
   if (Token.is(MIToken::Identifier) && Token.stringValue() == "unsized") {
-    if (MustBeSized)
-      return error(Loc, "expected pN, sN or <N x sM> for sized GlobalISel type");
     lex();
     Ty = LLT::unsized();
     return false;

diff --git a/llvm/test/CodeGen/MIR/X86/generic-instr-type-error.mir b/llvm/test/CodeGen/MIR/X86/generic-instr-type-error.mir
deleted file mode 100644 (file)
index b6ebb6c..0000000
--- a/llvm/test/CodeGen/MIR/X86/generic-instr-type-error.mir
+++ /dev/null
@@ -1,15 +0,0 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# This test ensures that the MIR parser report an error for
-# opaque types used on generic instruction.
-
----
-name:            bar
-isSSA:           true
-registers:
-  - { id: 0, class: gr32 }
-body: |
-  bb.0.entry:
-    liveins: %edi
-    ; CHECK: [[@LINE+1]]:16: expected pN, sN or <N x sM> for sized GlobalISel type
-    %0 = G_ADD unsized %edi, %edi
-...

diff --git a/llvm/test/CodeGen/MIR/X86/generic-virtual-registers.mir b/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
similarity index 76%
rename from llvm/test/CodeGen/MIR/X86/generic-virtual-registers.mir
rename to llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
index 09dc3ae..8545acc 100644 (file)
--- a/llvm/test/CodeGen/MIR/X86/generic-virtual-registers.mir
+++ b/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
@@ -1,22 +1,23 @@
 # RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
 # REQUIRES: global-isel
-# This test ensures that the MIR parser parses generic virtual
-# register definitions correctly.
+# Test that the MIR parser parses types on generic instructions correctly.
 
 --- |
-  ; ModuleID = 'generic-virtual-registers-type-error.mir'
   target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
   %type_alias = type <2 x i32>
   %structure_alias = type { i32, i16 }
-  define void @bar() {
-  entry:
+  define void @test_vregs() {
+    ret void
+  }
+
+  define void @test_unsized() {
     ret void
   }
 
 ...
 
 ---
-name:            bar
+name:            test_vregs
 isSSA:           true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: _ }
@@ -31,7 +32,7 @@ registers:
   - { id: 3, class: _ }
   - { id: 4, class: _ }
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: %edi
     ; CHECK:      %0(32) = G_ADD s32 %edi
     %0(32) = G_ADD s32 %edi, %edi
@@ -46,3 +47,14 @@ body: |
     ; CHECK:      %4(48) = G_ADD s48 %edi
     %4(48) = G_ADD s48 %edi, %edi
 ...
+
+---
+name:            test_unsized
+isSSA:           true
+body: |
+  bb.0:
+    successors: %bb.0
+
+    ; CHECK:      G_BR unsized %bb.0
+    G_BR unsized %bb.0
+...