static INLINE uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
{
-#ifdef PIPE_ARCH_BIG_ENDIAN
- switch(colorformat) {
- case V_028C70_COLOR_4_4:
- return(ENDIAN_NONE);
-
- /* 8-bit buffers. */
- case V_028C70_COLOR_8:
- return(ENDIAN_NONE);
-
- /* 16-bit buffers. */
- case V_028C70_COLOR_5_6_5:
- case V_028C70_COLOR_1_5_5_5:
- case V_028C70_COLOR_4_4_4_4:
- case V_028C70_COLOR_16:
- case V_028C70_COLOR_8_8:
- return(ENDIAN_8IN16);
-
- /* 32-bit buffers. */
- case V_028C70_COLOR_8_8_8_8:
- case V_028C70_COLOR_2_10_10_10:
- case V_028C70_COLOR_8_24:
- case V_028C70_COLOR_24_8:
- case V_028C70_COLOR_32_FLOAT:
- case V_028C70_COLOR_16_16_FLOAT:
- case V_028C70_COLOR_16_16:
- return(ENDIAN_8IN32);
-
- /* 64-bit buffers. */
- case V_028C70_COLOR_16_16_16_16:
- case V_028C70_COLOR_16_16_16_16_FLOAT:
- return(ENDIAN_8IN16);
-
- case V_028C70_COLOR_32_32_FLOAT:
- case V_028C70_COLOR_32_32:
- return(ENDIAN_8IN32);
-
- /* 128-bit buffers. */
- case V_028C70_COLOR_32_32_32_FLOAT:
- case V_028C70_COLOR_32_32_32_32_FLOAT:
- case V_028C70_COLOR_32_32_32_32:
- return(ENDIAN_8IN32);
- default:
- return ENDIAN_NONE; /* Unsupported. */
+ if (R600_BIG_ENDIAN) {
+ switch(colorformat) {
+ case V_028C70_COLOR_4_4:
+ return(ENDIAN_NONE);
+
+ /* 8-bit buffers. */
+ case V_028C70_COLOR_8:
+ return(ENDIAN_NONE);
+
+ /* 16-bit buffers. */
+ case V_028C70_COLOR_5_6_5:
+ case V_028C70_COLOR_1_5_5_5:
+ case V_028C70_COLOR_4_4_4_4:
+ case V_028C70_COLOR_16:
+ case V_028C70_COLOR_8_8:
+ return(ENDIAN_8IN16);
+
+ /* 32-bit buffers. */
+ case V_028C70_COLOR_8_8_8_8:
+ case V_028C70_COLOR_2_10_10_10:
+ case V_028C70_COLOR_8_24:
+ case V_028C70_COLOR_24_8:
+ case V_028C70_COLOR_32_FLOAT:
+ case V_028C70_COLOR_16_16_FLOAT:
+ case V_028C70_COLOR_16_16:
+ return(ENDIAN_8IN32);
+
+ /* 64-bit buffers. */
+ case V_028C70_COLOR_16_16_16_16:
+ case V_028C70_COLOR_16_16_16_16_FLOAT:
+ return(ENDIAN_8IN16);
+
+ case V_028C70_COLOR_32_32_FLOAT:
+ case V_028C70_COLOR_32_32:
+ return(ENDIAN_8IN32);
+
+ /* 128-bit buffers. */
+ case V_028C70_COLOR_32_32_32_FLOAT:
+ case V_028C70_COLOR_32_32_32_32_FLOAT:
+ case V_028C70_COLOR_32_32_32_32:
+ return(ENDIAN_8IN32);
+ default:
+ return ENDIAN_NONE; /* Unsupported. */
+ }
+ } else {
+ return ENDIAN_NONE;
}
-#else
- return ENDIAN_NONE;
-#endif
}
static INLINE boolean r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
-#ifdef PIPE_ARCH_BIG_ENDIAN
- S_030008_ENDIAN_SWAP(ENDIAN_8IN32) |
-#endif
+ S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
S_030008_STRIDE(stride), 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
#include "r600_formats.h"
#include "r600d.h"
-#ifdef PIPE_ARCH_BIG_ENDIAN
-#define CPU_TO_LE32(x) bswap_32(x)
-#else
-#define CPU_TO_LE32(x) (x)
-#endif
-
#define NUM_OF_CYCLES 3
#define NUM_OF_COMPONENTS 4
S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
bc->bytecode[id++] = S_SQ_VTX_WORD2_OFFSET(vtx->offset) |
- S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian) |
+ S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian) |
S_SQ_VTX_WORD2_MEGA_FETCH(1);
bc->bytecode[id++] = 0;
return 0;
}
}
+ *endian = r600_endian_swap(desc->channel[i].size);
+
switch (desc->channel[i].type) {
/* Half-floats, floats, ints */
case UTIL_FORMAT_TYPE_FLOAT:
*format = FMT_16_16_16_16_FLOAT;
break;
}
-#ifdef PIPE_ARCH_BIG_ENDIAN
- *endian = ENDIAN_8IN16;
-#endif
break;
case 32:
switch (desc->nr_channels) {
*format = FMT_32_32_32_32_FLOAT;
break;
}
-#ifdef PIPE_ARCH_BIG_ENDIAN
- *endian = ENDIAN_8IN32;
-#endif
break;
default:
goto out_unknown;
*format = FMT_16_16_16_16;
break;
}
-#ifdef PIPE_ARCH_BIG_ENDIAN
- *endian = ENDIAN_8IN16;
-#endif
break;
case 32:
switch (desc->nr_channels) {
*format = FMT_32_32_32_32;
break;
}
-#ifdef PIPE_ARCH_BIG_ENDIAN
- *endian = ENDIAN_8IN32;
-#endif
break;
default:
goto out_unknown;
return -ENOMEM;
}
- for(i = 0; i < ve->fs_size / 4; i++) {
- *(bytecode + i) = CPU_TO_LE32(*(bc.bytecode + i));
+ if (R600_BIG_ENDIAN) {
+ for (i = 0; i < ve->fs_size / 4; ++i) {
+ bytecode[i] = bswap_32(bc.bytecode[i]);
+ }
+ } else {
+ memcpy(bytecode, bc.bytecode, ve->fs_size);
}
r600_bo_unmap(rctx->radeon, ve->fetch_shader);
uint8_t *ptr = (*rbuffer)->r.b.user_ptr;
unsigned size = (*rbuffer)->r.b.b.b.width0;
boolean flushed;
-#ifdef PIPE_ARCH_BIG_ENDIAN
- int i;
- uint32_t *tmpPtr;
*rbuffer = NULL;
- tmpPtr = (uint32_t *)malloc(size);
- /* big endian swap */
- if(tmpPtr == NULL) {
- return;
- }
- for(i = 0; i < size / 4; i++) {
- tmpPtr[i] = bswap_32(*((uint32_t *)ptr + i));
- }
+ if (R600_BIG_ENDIAN) {
+ uint32_t *tmpPtr;
+ unsigned i;
- u_upload_data(rctx->vbuf_mgr->uploader, 0, size, tmpPtr, const_offset,
- (struct pipe_resource**)rbuffer, &flushed);
+ if (!(tmpPtr = malloc(size))) {
+ R600_ERR("Failed to allocate BE swap buffer.\n");
+ return;
+ }
- free(tmpPtr);
-#else
- *rbuffer = NULL;
+ for (i = 0; i < size / 4; ++i) {
+ tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
+ }
- u_upload_data(rctx->vbuf_mgr->uploader, 0, size, ptr, const_offset,
- (struct pipe_resource**)rbuffer, &flushed);
-#endif
+ u_upload_data(rctx->vbuf_mgr->uploader, 0, size, tmpPtr, const_offset,
+ (struct pipe_resource**)rbuffer, &flushed);
+
+ free(tmpPtr);
+ } else {
+ u_upload_data(rctx->vbuf_mgr->uploader, 0, size, ptr, const_offset,
+ (struct pipe_resource**)rbuffer, &flushed);
+ }
} else {
*const_offset = 0;
}
#ifndef R600_FORMATS_H
#define R600_FORMATS_H
+#include "r600_pipe.h"
+
/* list of formats from R700 ISA document - apply across GPUs in different registers */
#define FMT_INVALID 0x00000000
#define FMT_8 0x00000001
#define FMT_BC4 0x00000034
#define FMT_BC5 0x00000035
+#define ENDIAN_NONE 0
+#define ENDIAN_8IN16 1
+#define ENDIAN_8IN32 2
+#define ENDIAN_8IN64 3
+
+static INLINE unsigned r600_endian_swap(unsigned size)
+{
+ if (R600_BIG_ENDIAN) {
+ switch (size) {
+ case 64:
+ return ENDIAN_8IN64;
+ case 32:
+ return ENDIAN_8IN32;
+ case 16:
+ return ENDIAN_8IN16;
+ default:
+ return ENDIAN_NONE;
+ }
+ } else {
+ return ENDIAN_NONE;
+ }
+}
+
#endif
#define R600_MAX_CONST_BUFFERS 1
#define R600_MAX_CONST_BUFFER_SIZE 4096
+#ifdef PIPE_ARCH_BIG_ENDIAN
+#define R600_BIG_ENDIAN 1
+#else
+#define R600_BIG_ENDIAN 0
+#endif
+
enum r600_pipe_state_id {
R600_PIPE_STATE_BLEND = 0,
R600_PIPE_STATE_BLEND_COLOR,
#include <errno.h>
#include <byteswap.h>
-#ifdef PIPE_ARCH_BIG_ENDIAN
-#define CPU_TO_LE32(x) bswap_32(x)
-#else
-#define CPU_TO_LE32(x) (x)
-#endif
-
int r600_find_vs_semantic_index(struct r600_shader *vs,
struct r600_shader *ps, int id)
{
return -ENOMEM;
}
ptr = (uint32_t*)r600_bo_map(rctx->radeon, shader->bo, 0, NULL);
- for(i = 0; i < rshader->bc.ndw; i++) {
- *(ptr + i) = CPU_TO_LE32(*(rshader->bc.bytecode + i));
+ if (R600_BIG_ENDIAN) {
+ for (i = 0; i < rshader->bc.ndw; ++i) {
+ ptr[i] = bswap_32(rshader->bc.bytecode[i]);
+ }
+ } else {
+ memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * sizeof(*ptr));
}
r600_bo_unmap(rctx->radeon, shader->bo);
}
vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
-#ifdef PIPE_ARCH_BIG_ENDIAN
- vtx.endian = ENDIAN_8IN32;
-#else
- vtx.endian = ENDIAN_NONE;
-#endif
+ vtx.endian = r600_endian_swap(32);
if ((r = r600_bc_add_vtx(ctx->bc, &vtx)))
return r;
r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
-#ifdef PIPE_ARCH_BIG_ENDIAN
- S_038008_ENDIAN_SWAP(ENDIAN_8IN32) |
-#endif
+ S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
S_038008_STRIDE(stride), 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
0x00000000, 0xFFFFFFFF, NULL);
#include <util/u_format.h>
#include <pipebuffer/pb_buffer.h>
#include "pipe/p_shader_tokens.h"
+#include "r600_formats.h"
#include "r600_pipe.h"
#include "r600d.h"
case 2:
vgt_draw_initiator = 0;
vgt_dma_index_type = 0;
-#ifdef PIPE_ARCH_BIG_ENDIAN
- vgt_dma_swap_mode = ENDIAN_8IN16;
-#endif
+ if (R600_BIG_ENDIAN) {
+ vgt_dma_swap_mode = ENDIAN_8IN16;
+ }
break;
case 4:
vgt_draw_initiator = 0;
vgt_dma_index_type = 1;
-#ifdef PIPE_ARCH_BIG_ENDIAN
- vgt_dma_swap_mode = ENDIAN_8IN32;
-#endif
+ if (R600_BIG_ENDIAN) {
+ vgt_dma_swap_mode = ENDIAN_8IN32;
+ }
break;
case 0:
vgt_draw_initiator = 2;
static INLINE uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
{
-#ifdef PIPE_ARCH_BIG_ENDIAN
- switch(colorformat) {
- case V_0280A0_COLOR_4_4:
- return(ENDIAN_NONE);
-
- /* 8-bit buffers. */
- case V_0280A0_COLOR_8:
- return(ENDIAN_NONE);
-
- /* 16-bit buffers. */
- case V_0280A0_COLOR_5_6_5:
- case V_0280A0_COLOR_1_5_5_5:
- case V_0280A0_COLOR_4_4_4_4:
- case V_0280A0_COLOR_16:
- case V_0280A0_COLOR_8_8:
- return(ENDIAN_8IN16);
-
- /* 32-bit buffers. */
- case V_0280A0_COLOR_8_8_8_8:
- case V_0280A0_COLOR_2_10_10_10:
- case V_0280A0_COLOR_8_24:
- case V_0280A0_COLOR_24_8:
- case V_0280A0_COLOR_32_FLOAT:
- case V_0280A0_COLOR_16_16_FLOAT:
- case V_0280A0_COLOR_16_16:
- return(ENDIAN_8IN32);
-
- /* 64-bit buffers. */
- case V_0280A0_COLOR_16_16_16_16:
- case V_0280A0_COLOR_16_16_16_16_FLOAT:
- return(ENDIAN_8IN16);
-
- case V_0280A0_COLOR_32_32_FLOAT:
- case V_0280A0_COLOR_32_32:
- return(ENDIAN_8IN32);
-
- /* 128-bit buffers. */
- case V_0280A0_COLOR_32_32_32_FLOAT:
- case V_0280A0_COLOR_32_32_32_32_FLOAT:
- case V_0280A0_COLOR_32_32_32_32:
- return(ENDIAN_8IN32);
- default:
- return ENDIAN_NONE; /* Unsupported. */
+ if (R600_BIG_ENDIAN) {
+ switch(colorformat) {
+ case V_0280A0_COLOR_4_4:
+ return(ENDIAN_NONE);
+
+ /* 8-bit buffers. */
+ case V_0280A0_COLOR_8:
+ return(ENDIAN_NONE);
+
+ /* 16-bit buffers. */
+ case V_0280A0_COLOR_5_6_5:
+ case V_0280A0_COLOR_1_5_5_5:
+ case V_0280A0_COLOR_4_4_4_4:
+ case V_0280A0_COLOR_16:
+ case V_0280A0_COLOR_8_8:
+ return(ENDIAN_8IN16);
+
+ /* 32-bit buffers. */
+ case V_0280A0_COLOR_8_8_8_8:
+ case V_0280A0_COLOR_2_10_10_10:
+ case V_0280A0_COLOR_8_24:
+ case V_0280A0_COLOR_24_8:
+ case V_0280A0_COLOR_32_FLOAT:
+ case V_0280A0_COLOR_16_16_FLOAT:
+ case V_0280A0_COLOR_16_16:
+ return(ENDIAN_8IN32);
+
+ /* 64-bit buffers. */
+ case V_0280A0_COLOR_16_16_16_16:
+ case V_0280A0_COLOR_16_16_16_16_FLOAT:
+ return(ENDIAN_8IN16);
+
+ case V_0280A0_COLOR_32_32_FLOAT:
+ case V_0280A0_COLOR_32_32:
+ return(ENDIAN_8IN32);
+
+ /* 128-bit buffers. */
+ case V_0280A0_COLOR_32_32_32_FLOAT:
+ case V_0280A0_COLOR_32_32_32_32_FLOAT:
+ case V_0280A0_COLOR_32_32_32_32:
+ return(ENDIAN_8IN32);
+ default:
+ return ENDIAN_NONE; /* Unsupported. */
+ }
+ } else {
+ return ENDIAN_NONE;
}
-#else
- return ENDIAN_NONE;
-#endif
}
static INLINE boolean r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
#define SQ_TEX_INST_SAMPLE_L 0x11
#define SQ_TEX_INST_SAMPLE_C 0x18
-#define ENDIAN_NONE 0
-#define ENDIAN_8IN16 1
-#define ENDIAN_8IN32 2
-#define ENDIAN_8IN64 3
-
#endif
projects / platform / upstream / mesa.git / commitdiff