&& (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2ADD) == 0)
rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2ADD;
+ if (TARGET_POWER10
+ && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2STORE) == 0)
+ rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2STORE;
+
/* Turn off vector pair/mma options on non-power10 systems. */
else if (!TARGET_POWER10 && TARGET_MMA)
{
return cached_can_issue_more;
}
+/* Determine if INSN is a store to memory that can be fused with a similar
+ adjacent store. */
+
+static bool
+is_fusable_store (rtx_insn *insn, rtx *str_mem)
+{
+ /* Insn must be a non-prefixed base+disp form store. */
+ if (is_store_insn (insn, str_mem)
+ && get_attr_prefixed (insn) == PREFIXED_NO
+ && get_attr_update (insn) == UPDATE_NO
+ && get_attr_indexed (insn) == INDEXED_NO)
+ {
+ /* Further restrictions by mode and size. */
+ if (!MEM_SIZE_KNOWN_P (*str_mem))
+ return false;
+
+ machine_mode mode = GET_MODE (*str_mem);
+ HOST_WIDE_INT size = MEM_SIZE (*str_mem);
+
+ if (INTEGRAL_MODE_P (mode))
+ /* Must be word or dword size. */
+ return (size == 4 || size == 8);
+ else if (FLOAT_MODE_P (mode))
+ /* Must be dword size. */
+ return (size == 8);
+ }
+
+ return false;
+}
+
+/* Do Power10 specific reordering of the ready list. */
+
+static int
+power10_sched_reorder (rtx_insn **ready, int lastpos)
+{
+ rtx mem1;
+
+ /* Do store fusion during sched2 only. */
+ if (!reload_completed)
+ return cached_can_issue_more;
+
+ /* If the prior insn finished off a store fusion pair then simply
+ reset the counter and return, nothing more to do. */
+ if (load_store_pendulum != 0)
+ {
+ load_store_pendulum = 0;
+ return cached_can_issue_more;
+ }
+
+ /* Try to pair certain store insns to adjacent memory locations
+ so that the hardware will fuse them to a single operation. */
+ if (TARGET_P10_FUSION && TARGET_P10_FUSION_2STORE
+ && is_fusable_store (last_scheduled_insn, &mem1))
+ {
+
+ /* A fusable store was just scheduled. Scan the ready list for another
+ store that it can fuse with. */
+ int pos = lastpos;
+ while (pos >= 0)
+ {
+ rtx mem2;
+ /* GPR stores can be ascending or descending offsets, FPR/VSR stores
+ must be ascending only. */
+ if (is_fusable_store (ready[pos], &mem2)
+ && ((INTEGRAL_MODE_P (GET_MODE (mem1))
+ && adjacent_mem_locations (mem1, mem2))
+ || (FLOAT_MODE_P (GET_MODE (mem1))
+ && (adjacent_mem_locations (mem1, mem2) == mem1))))
+ {
+ /* Found a fusable store. Move it to the end of the ready list
+ so it is scheduled next. */
+ move_to_end_of_ready (ready, pos, lastpos);
+
+ load_store_pendulum = -1;
+ break;
+ }
+ pos--;
+ }
+ }
+
+ return cached_can_issue_more;
+}
+
/* We are about to begin issuing insns for this clock cycle. */
static int
if (rs6000_tune == PROCESSOR_POWER6)
load_store_pendulum = 0;
+ /* Do Power10 dependent reordering. */
+ if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn)
+ power10_sched_reorder (ready, n_ready - 1);
+
return rs6000_issue_rate ();
}
&& recog_memoized (last_scheduled_insn) >= 0)
return power9_sched_reorder2 (ready, *pn_ready - 1);
+ /* Do Power10 dependent reordering. */
+ if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn)
+ return power10_sched_reorder (ready, *pn_ready - 1);
+
return cached_can_issue_more;
}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
+
+/* Verify store fusion is enabled */
+
+void fuse_stw (int *i, int a, int b, int c)
+{
+ i[1] = a;
+ i[5] = b;
+ i[2] = c;
+}
+
+void fuse_std (long *i, long a, long b, long c)
+{
+ i[1] = a;
+ i[5] = b;
+ i[2] = c;
+}
+
+void fuse_stfd (double *i, double a, double b, double c)
+{
+ i[1] = a;
+ i[5] = b;
+ i[2] = c;
+}
+
+/* { dg-final { scan-assembler-times {stw 4,4\(3\)\n\tstw 6,8\(3\)} 1 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {stw 4,4\(3\)\n\tstw 6,8\(3\)} 2 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {std 4,8\(3\)\n\tstd 6,16\(3\)} 1 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {stfd 1,8\(3\)\n\tstfd 3,16\(3\)} 1 } } */
+
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=power10 -mno-power10-fusion -O2" } */
+
+/* Verify store fusion is disabled */
+
+void fuse_stw (int *i, int a, int b, int c)
+{
+ i[1] = a;
+ i[5] = b;
+ i[2] = c;
+}
+
+void fuse_std (long *i, long a, long b, long c)
+{
+ i[1] = a;
+ i[5] = b;
+ i[2] = c;
+}
+
+void fuse_stfd (double *i, double a, double b, double c)
+{
+ i[1] = a;
+ i[5] = b;
+ i[2] = c;
+}
+
+
+/* { dg-final { scan-assembler-not {stw 4,4\(3\)\n\tstw 6,8\(3\)} } } */
+/* { dg-final { scan-assembler-not {std 4,8\(3\)\n\tstd 6,16\(3\)} { target lp64 } } } */
+/* { dg-final { scan-assembler-not {stfd 1,8\(3\)\n\tstfd 3,16\(3\)} } } */