arm64: mte: CPU feature detection for Asymm MTE
authorVincenzo Frascino <vincenzo.frascino@arm.com>
Wed, 6 Oct 2021 15:47:49 +0000 (16:47 +0100)
committerWill Deacon <will@kernel.org>
Thu, 7 Oct 2021 08:21:57 +0000 (09:21 +0100)
Add the cpufeature entries to detect the presence of Asymmetric MTE.

Note: The tag checking mode is initialized via cpu_enable_mte() ->
kasan_init_hw_tags() hence to enable it we require asymmetric mode
to be at least on the boot CPU. If the boot CPU does not have it, it is
fine for late CPUs to have it as long as the feature is not enabled
(ARM64_CPUCAP_BOOT_CPU_FEATURE).

Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20211006154751.4463-4-vincenzo.frascino@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
arch/arm64/kernel/cpufeature.c
arch/arm64/tools/cpucaps

index 6ec7036ef7e1808eca4b63973cdecf12b0d25c16..9e3e8ad75f209e417f4dbd4062cc8e9e946b95f4 100644 (file)
@@ -2321,6 +2321,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
                .sign = FTR_UNSIGNED,
                .cpu_enable = cpu_enable_mte,
        },
+       {
+               .desc = "Asymmetric MTE Tag Check Fault",
+               .capability = ARM64_MTE_ASYMM,
+               .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
+               .matches = has_cpuid_feature,
+               .sys_reg = SYS_ID_AA64PFR1_EL1,
+               .field_pos = ID_AA64PFR1_MTE_SHIFT,
+               .min_field_value = ID_AA64PFR1_MTE_ASYMM,
+               .sign = FTR_UNSIGNED,
+       },
 #endif /* CONFIG_ARM64_MTE */
        {
                .desc = "RCpc load-acquire (LDAPR)",
index 49305c2e6dfd3179e8f877141ab757bf6c81aea5..74a569bf52d6e59932d39cb08d51ddba6efe8293 100644 (file)
@@ -39,6 +39,7 @@ HW_DBM
 KVM_PROTECTED_MODE
 MISMATCHED_CACHE_TYPE
 MTE
+MTE_ASYMM
 SPECTRE_V2
 SPECTRE_V3A
 SPECTRE_V4