drm/amdgpu/gfx9: store the eop gpu addr in the ring structure

Avoids passing around additional parameters during setup.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 74c762d..ce0d74a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -613,6 +613,7 @@ static int gfx_v9_0_kiq_init_ring(struct amdgpu_device *adev,
                                  struct amdgpu_ring *ring,
                                  struct amdgpu_irq_src *irq)
 {
+       struct amdgpu_kiq *kiq = &adev->gfx.kiq;
        int r = 0;
 
        r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs);
@@ -633,6 +634,7 @@ static int gfx_v9_0_kiq_init_ring(struct amdgpu_device *adev,
 
        irq->data = ring;
        ring->queue = 0;
+       ring->eop_gpu_addr = kiq->eop_gpu_addr;
        sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue);
        r = amdgpu_ring_init(adev, ring, 1024,
                             irq, AMDGPU_CP_KIQ_IRQ_DRIVER0);
@@ -1094,6 +1096,7 @@ static int gfx_v9_0_sw_init(void *handle)
                ring->me = 1; /* first MEC */
                ring->pipe = i / 8;
                ring->queue = i % 8;
+               ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
                sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
                irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
                /* type-2 packets are deprecated on MEC, use type-3 instead */
@@ -1892,8 +1895,7 @@ static void gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring,
 }
 
 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring,
-                            struct v9_mqd *mqd,
-                            uint64_t eop_gpu_addr)
+                            struct v9_mqd *mqd)
 {
        struct amdgpu_device *adev = ring->adev;
        uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
@@ -1907,7 +1909,7 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring,
        mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
        mqd->compute_misc_reserved = 0x00000003;
 
-       eop_base_addr = eop_gpu_addr >> 8;
+       eop_base_addr = ring->eop_gpu_addr >> 8;
        mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
        mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
 
@@ -2134,16 +2136,12 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring,
 {
        struct amdgpu_device *adev = ring->adev;
        struct amdgpu_kiq *kiq = &adev->gfx.kiq;
-       uint64_t eop_gpu_addr;
        bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ);
        int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
 
        if (is_kiq) {
-               eop_gpu_addr = kiq->eop_gpu_addr;
                gfx_v9_0_kiq_setting(&kiq->ring);
        } else {
-               eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr +
-                                       ring->queue * MEC_HPD_SIZE;
                mqd_idx = ring - &adev->gfx.compute_ring[0];
        }
 
@@ -2151,7 +2149,7 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring,
                memset((void *)mqd, 0, sizeof(*mqd));
                mutex_lock(&adev->srbm_mutex);
                soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
-               gfx_v9_0_mqd_init(ring, mqd, eop_gpu_addr);
+               gfx_v9_0_mqd_init(ring, mqd);
                if (is_kiq)
                        gfx_v9_0_kiq_init_register(ring, mqd);
                soc15_grbm_select(adev, 0, 0, 0, 0);