const MachineRegisterInfo &MRI) {
assert(I.getOpcode() == TargetOpcode::REG_SEQUENCE);
unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm();
- auto *DstRC = MRI.getRegClass(I.getOperand(0).getReg());
+ auto &DstRC = *MRI.getRegClass(I.getOperand(0).getReg());
auto &HRI = static_cast<const HexagonRegisterInfo&>(
*MRI.getTargetRegisterInfo());
unsigned SubLo = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_lo);
auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void {
(void)HRI;
- assert(Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo) ||
- Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi));
+ assert(Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_lo) ||
+ Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_hi));
};
switch (RC->getID()) {
if (FRC == &Hexagon::DoubleRegsRegClass ||
FRC == &Hexagon::HvxWRRegClass) {
// Try to generate REG_SEQUENCE.
- unsigned SubLo = HRI.getHexagonSubRegIndex(FRC, Hexagon::ps_sub_lo);
- unsigned SubHi = HRI.getHexagonSubRegIndex(FRC, Hexagon::ps_sub_hi);
+ unsigned SubLo = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_lo);
+ unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi);
BitTracker::RegisterRef TL = { R, SubLo };
BitTracker::RegisterRef TH = { R, SubHi };
BitTracker::RegisterRef ML, MH;
case TargetOpcode::REG_SEQUENCE: {
BitTracker::RegisterRef SL, SH;
if (HBS::parseRegSequence(MI, SL, SH, MRI)) {
- const TargetRegisterClass *RC = MRI.getRegClass(RD.Reg);
+ const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg);
unsigned SubLo = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo);
unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi);
Changed = HBS::replaceSubWithSub(RD.Reg, SubLo, SL.Reg, SL.Sub, MRI);
}
case Hexagon::A2_combinew:
case Hexagon::V6_vcombine: {
- const TargetRegisterClass *RC = MRI.getRegClass(RD.Reg);
+ const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg);
unsigned SubLo = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo);
unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi);
BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2);
if (Sub == 0)
return MachineEvaluator::mask(Reg, 0);
- const TargetRegisterClass *RC = MRI.getRegClass(Reg);
- unsigned ID = RC->getID();
+ const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
+ unsigned ID = RC.getID();
uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
break;
}
#ifndef NDEBUG
- dbgs() << PrintReg(Reg, &TRI, Sub) << '\n';
+ dbgs() << PrintReg(Reg, &TRI, Sub) << " in reg class "
+ << TRI.getRegClassName(&RC) << '\n';
#endif
llvm_unreachable("Unexpected register/subregister");
}
unsigned HexagonRegisterInfo::getHexagonSubRegIndex(
- const TargetRegisterClass *RC, unsigned GenIdx) const {
+ const TargetRegisterClass &RC, unsigned GenIdx) const {
assert(GenIdx == Hexagon::ps_sub_lo || GenIdx == Hexagon::ps_sub_hi);
static const unsigned ISub[] = { Hexagon::isub_lo, Hexagon::isub_hi };
static const unsigned VSub[] = { Hexagon::vsub_lo, Hexagon::vsub_hi };
- switch (RC->getID()) {
+ switch (RC.getID()) {
case Hexagon::CtrRegs64RegClassID:
case Hexagon::DoubleRegsRegClassID:
return ISub[GenIdx];
return VSub[GenIdx];
}
- if (const TargetRegisterClass *SuperRC = *RC->getSuperClasses())
- return getHexagonSubRegIndex(SuperRC, GenIdx);
+ if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses())
+ return getHexagonSubRegIndex(*SuperRC, GenIdx);
llvm_unreachable("Invalid register class");
}