drm/amdgpu/vcn: custom video info caps for sriov

for sriov, we added a new flag to indicate av1 support,
this will override the original caps info.

Signed-off-by: Jane Jian <Jane.Jian@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index b9e9480..4f7bab5 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -124,6 +124,8 @@ enum AMDGIM_FEATURE_FLAG {
        AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
        /* Indirect Reg Access enabled */
        AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5),
+       /* AV1 Support MODE*/
+       AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6),
 };
 
 enum AMDGIM_REG_ACCESS_FLAG {
@@ -322,6 +324,8 @@ static inline bool is_virtual_machine(void)
        ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
 #define amdgpu_sriov_is_normal(adev) \
        ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
+#define amdgpu_sriov_is_av1_support(adev) \
+       ((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT)
 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
 void amdgpu_virt_init_setting(struct amdgpu_device *adev);
 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
index 6c97148..24d42d2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
@@ -93,7 +93,8 @@ union amd_sriov_msg_feature_flags {
                uint32_t mm_bw_management  : 1;
                uint32_t pp_one_vf_mode    : 1;
                uint32_t reg_indirect_acc  : 1;
-               uint32_t reserved          : 26;
+               uint32_t av1_support       : 1;
+               uint32_t reserved          : 25;
        } flags;
        uint32_t all;
 };

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 061793d..c82b3a7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -102,6 +102,59 @@ static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 =
        .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1,
 };
 
+/* SRIOV SOC21, not const since data is controlled by host */
+static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
+};
+
+static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
+};
+
+static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = {
+       .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
+       .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
+};
+
+static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = {
+       .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
+       .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
+};
+
+static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
+};
+
+static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
+       {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
+};
+
+static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = {
+       .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0),
+       .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
+};
+
+static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = {
+       .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1),
+       .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
+};
+
 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
                                 const struct amdgpu_video_codecs **codecs)
 {
@@ -112,16 +165,31 @@ static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
        case IP_VERSION(4, 0, 0):
        case IP_VERSION(4, 0, 2):
        case IP_VERSION(4, 0, 4):
-               if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
-                       if (encode)
-                               *codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
-                       else
-                               *codecs = &vcn_4_0_0_video_codecs_decode_vcn1;
+               if (amdgpu_sriov_vf(adev)) {
+                       if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
+                       !amdgpu_sriov_is_av1_support(adev)) {
+                               if (encode)
+                                       *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1;
+                               else
+                                       *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1;
+                       } else {
+                               if (encode)
+                                       *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0;
+                               else
+                                       *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0;
+                       }
                } else {
-                       if (encode)
-                               *codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
-                       else
-                               *codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
+                       if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) {
+                               if (encode)
+                                       *codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
+                               else
+                                       *codecs = &vcn_4_0_0_video_codecs_decode_vcn1;
+                       } else {
+                               if (encode)
+                                       *codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
+                               else
+                                       *codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
+                       }
                }
                return 0;
        default:
@@ -730,8 +798,23 @@ static int soc21_common_late_init(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-       if (amdgpu_sriov_vf(adev))
+       if (amdgpu_sriov_vf(adev)) {
                xgpu_nv_mailbox_get_irq(adev);
+               if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
+               !amdgpu_sriov_is_av1_support(adev)) {
+                       amdgpu_virt_update_sriov_video_codec(adev,
+                                                            sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
+                                                            ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
+                                                            sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
+                                                            ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1));
+               } else {
+                       amdgpu_virt_update_sriov_video_codec(adev,
+                                                            sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
+                                                            ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
+                                                            sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
+                                                            ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0));
+               }
+       }
 
        return 0;
 }