[Hexagon] Add patterns for compares of i1 values

llvm-svn: 326220

diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index b0aaded4e986d8e714cc5618a3af8d4f7b9e1503..46bdafd228f87d003783690700b03fa6c7c0a887 100644 (file)
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -679,8 +679,10 @@ def: Pat<(i32 (zext (i1 (seteq I32:$Rs, anyimm:$s8)))),
 def: Pat<(i32 (zext (i1 (setne I32:$Rs, anyimm:$s8)))),
          (A4_rcmpneqi I32:$Rs, imm:$s8)>;
 
-def: Pat<(i1 (setne I1:$Ps, I1:$Pt)),
-         (C2_xor I1:$Ps, I1:$Pt)>;
+def: Pat<(i1 (seteq I1:$Ps, (i1 -1))), (I1:$Ps)>;
+def: Pat<(i1 (setne I1:$Ps, (i1 -1))), (C2_not I1:$Ps)>;
+def: Pat<(i1 (seteq I1:$Ps, I1:$Pt)),  (C2_xor I1:$Ps, (C2_not I1:$Pt))>;
+def: Pat<(i1 (setne I1:$Ps, I1:$Pt)),  (C2_xor I1:$Ps, I1:$Pt)>;
 
 def: Pat<(i1 (seteq V4I8:$Rs, V4I8:$Rt)),
          (A2_vcmpbeq (ToZext64 $Rs), (ToZext64 $Rt))>;

diff --git a/llvm/test/CodeGen/Hexagon/isel-setcc-i1.ll b/llvm/test/CodeGen/Hexagon/isel-setcc-i1.ll
new file mode 100644 (file)
index 0000000..8201c73
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/isel-setcc-i1.ll
@@ -0,0 +1,27 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Check that this compiles successfully.
+; CHECK: if (p0)
+
+target triple = "hexagon"
+
+define void @fred() #0 {
+b0:
+  br label %b1
+
+b1:                                               ; preds = %b1, %b0
+  %v2 = load i32, i32* undef, align 4
+  %v3 = select i1 undef, i32 %v2, i32 0
+  %v4 = and i32 %v3, 7
+  %v5 = icmp eq i32 %v4, 4
+  %v6 = or i1 undef, %v5
+  %v7 = and i1 undef, %v6
+  %v8 = xor i1 %v7, true
+  %v9 = or i1 undef, %v8
+  br i1 %v9, label %b10, label %b1
+
+b10:                                              ; preds = %b1
+  unreachable
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv55" }