drm/amd/pm: enable mode1 reset support for SMU 13.0.0

Fulfill the interfaces for mode1 reset related.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index fe9c47c..ba6adf0 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -302,5 +302,7 @@ int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu);
 
 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu);
+
+int smu_v13_0_mode1_reset(struct smu_context *smu);
 #endif
 #endif

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 0991c1f..f9c36d2 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2411,3 +2411,14 @@ void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu)
        smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
        smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
 }
+
+int smu_v13_0_mode1_reset(struct smu_context *smu)
+{
+       int ret = 0;
+
+       ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
+       if (!ret)
+               msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
+
+       return ret;
+}

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 2ee17b3..26fb72a 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -117,6 +117,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] =
        MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
        MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                 0),
        MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,           0),
+       MSG_MAP(Mode1Reset,                     PPSMC_MSG_Mode1Reset,                  0),
 };
 
 static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
@@ -1580,6 +1581,23 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu,
                                               NULL);
 }
 
+static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu)
+{
+       struct amdgpu_device *adev = smu->adev;
+       u32 smu_version;
+
+       /* SRIOV does not support SMU mode1 reset */
+       if (amdgpu_sriov_vf(adev))
+               return false;
+
+       /* PMFW support is available since 78.41 */
+       smu_cmn_get_smc_version(smu, NULL, &smu_version);
+       if (smu_version < 0x004e2900)
+               return false;
+
+       return true;
+}
+
 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
        .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
        .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
@@ -1642,6 +1660,8 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
        .baco_set_state = smu_v13_0_baco_set_state,
        .baco_enter = smu_v13_0_baco_enter,
        .baco_exit = smu_v13_0_baco_exit,
+       .mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported,
+       .mode1_reset = smu_v13_0_mode1_reset,
 };
 
 void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)