return def;
}
- Definition hint_${fixed}(Definition def) {
- % if fixed == 'vcc' or fixed == 'exec':
- //vcc_hi and exec_hi can still be used in wave32
- assert(def.regClass().type() == RegType::sgpr && def.bytes() <= 8);
- % endif
- def.setHint(aco::${fixed});
- return def;
- }
-
- Definition hint_${fixed}(RegClass rc) {
- return hint_${fixed}(def(rc));
- }
-
% endfor
Operand set16bit(Operand op) {
uint32_t identity_hi = get_reduction_identity(reduce_op, 1);
lo =
- bld.writelane(bld.def(v1), bld.copy(bld.hint_m0(s1), Operand::c32(identity_lo)), lane, lo);
+ bld.writelane(bld.def(v1), bld.copy(bld.def(s1, m0), Operand::c32(identity_lo)), lane, lo);
hi =
- bld.writelane(bld.def(v1), bld.copy(bld.hint_m0(s1), Operand::c32(identity_hi)), lane, hi);
+ bld.writelane(bld.def(v1), bld.copy(bld.def(s1, m0), Operand::c32(identity_hi)), lane, hi);
bld.pseudo(aco_opcode::p_create_vector, dst, lo, hi);
} else {
uint32_t identity = get_reduction_identity(reduce_op, 0);
- bld.writelane(dst, bld.copy(bld.hint_m0(s1), Operand::c32(identity)), lane,
+ bld.writelane(dst, bld.copy(bld.def(s1, m0), Operand::c32(identity)), lane,
as_vgpr(ctx, src));
}
class Definition final {
public:
constexpr Definition()
- : temp(Temp(0, s1)), reg_(0), isFixed_(0), hasHint_(0), isKill_(0), isPrecise_(0), isNUW_(0),
- isNoCSE_(0)
+ : temp(Temp(0, s1)), reg_(0), isFixed_(0), isKill_(0), isPrecise_(0), isNUW_(0), isNoCSE_(0)
{}
Definition(uint32_t index, RegClass type) noexcept : temp(index, type) {}
explicit Definition(Temp tmp) noexcept : temp(tmp) {}
reg_ = reg;
}
- constexpr void setHint(PhysReg reg) noexcept
- {
- hasHint_ = 1;
- reg_ = reg;
- }
-
- constexpr bool hasHint() const noexcept { return hasHint_; }
-
constexpr void setKill(bool flag) noexcept { isKill_ = flag; }
constexpr bool isKill() const noexcept { return isKill_; }
union {
struct {
uint8_t isFixed_ : 1;
- uint8_t hasHint_ : 1;
uint8_t isKill_ : 1;
uint8_t isPrecise_ : 1;
uint8_t isNUW_ : 1;