Merge branch 'topic/revid_steppings' into drm-intel-gt-next
authorMatt Roper <matthew.d.roper@intel.com>
Thu, 15 Jul 2021 00:54:25 +0000 (17:54 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Thu, 15 Jul 2021 00:55:21 +0000 (17:55 -0700)
The switch from old old IS_FOO_REVID() macros to the new table-based
IS_FOO_{GT,DISP}_STEP() macros is needed on both drm-intel-next (for
display-based DMC matching) and drm-intel-gt-next (for workaround
guards).  To avoid conflicts, we'll apply the patches to a topic branch
and merge it to both intel branches to ensure the transition to the
new macros is clean.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
1  2 
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
drivers/gpu/drm/i915/gt/intel_region_lmem.c
drivers/gpu/drm/i915/gt/intel_workarounds.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/intel_pm.c

@@@ -2674,8 -2674,8 +2674,8 @@@ static boo
  ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
  {
        return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
-                IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER)) ||
+                IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
 -               IS_TIGERLAKE(i915)) &&
 +               IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
                 i915->dpll.ref_clks.nssc == 38400;
  }
  
@@@ -990,18 -964,9 +938,9 @@@ icl_wa_init_mcr(struct drm_i915_privat
  }
  
  static void
- cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
- {
-       /* WaInPlaceDecompressionHang:cnl */
-       wa_write_or(wal,
-                   GEN9_GAMT_ECO_REG_RW_IA,
-                   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
- }
- static void
  icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
  {
 -      wa_init_mcr(i915, wal);
 +      icl_wa_init_mcr(i915, wal);
  
        /* WaInPlaceDecompressionHang:icl */
        wa_write_or(wal,
@@@ -1644,10 -1566,10 +1556,10 @@@ rcs_engine_wa_init(struct intel_engine_
                             FF_DOP_CLOCK_GATE_DISABLE);
        }
  
 -      if (IS_ALDERLAKE_S(i915) ||
 +      if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
-           IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+           IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
            IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
 -              /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s */
 +              /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
                wa_masked_en(wal, GEN7_ROW_CHICKEN2,
                             GEN12_PUSH_CONST_DEREF_HOLD_DIS);
  
Simple merge
Simple merge