+2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/tc-aarch64.c (parse_sys_ins_reg): Add check of
+ architectural support for system register.
+
2015-12-10 Jose E. Marchesi <jose.marchesi@oracle.com>
* doc/c-sparc.texi (Sparc-Regs): Document the %dN and %qN notation
if (!o)
return NULL;
+ if (!aarch64_sys_ins_reg_supported_p (cpu_variant, o))
+ as_bad (_("selected processor does not support system register "
+ "name '%s'"), buf);
+
*str = q;
return o;
}
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+ * gas/aarch64/sysreg-2.d: Add tests for dc instruction.
+ * gas/aarch64/sysreg-2.s: Add uses of dc instruction.
+
+2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+
* gas/aarch64/uao-directive.d: New.
* gas/aarch64/uao.d: New.
* gas/aarch64/uao.s: New.
[0-9a-f]+: d518c125 msr disr_el1, x5
[0-9a-f]+: d538c125 mrs x5, disr_el1
[0-9a-f]+: d53cc125 mrs x5, vdisr_el2
+ [0-9a-f]+: d50b7a20 dc cvac, x0
+ [0-9a-f]+: d50b7b21 dc cvau, x1
+ [0-9a-f]+: d50b7c22 dc cvap, x2
rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0
rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1
rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0
+
+ /* DC CVAP. */
+
+ dc cvac, x0
+ dc cvau, x1
+ dc cvap, x2
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+ * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
+
+2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+
* aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
(aarch64_sys_ins_reg_has_xt): Declare.
} aarch64_sys_ins_reg;
extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
+extern bfd_boolean
+aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
+ const aarch64_sys_ins_reg *);
extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+ * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
+ (aarch64_sys_ins_reg_supported_p): New.
+
+2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+
* aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
with aarch64_sys_ins_reg_has_xt.
(aarch64_ext_sysins_op): Likewise.
{ "cvac", CPENS (3, C7, C10, 1), F_HASXT },
{ "csw", CPENS (0, C7, C10, 2), F_HASXT },
{ "cvau", CPENS (3, C7, C11, 1), F_HASXT },
+ { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
{ "civac", CPENS (3, C7, C14, 1), F_HASXT },
{ "cisw", CPENS (0, C7, C14, 2), F_HASXT },
{ 0, CPENS(0,0,0,0), 0 }
return (sys_ins_reg->flags & F_HASXT) != 0;
}
+extern bfd_boolean
+aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
+ const aarch64_sys_ins_reg *reg)
+{
+ if (!(reg->flags & F_ARCHEXT))
+ return TRUE;
+
+ /* DC CVAP. Values are from aarch64_sys_regs_dc. */
+ if (reg->value == CPENS (3, C7, C12, 1)
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
+ return FALSE;
+
+ return TRUE;
+}
+
#undef C0
#undef C1
#undef C2