clk: mediatek: add the option for determining PLL source clock

[ Upstream commit c955bf3998efa3355790a4d8c82874582f1bc727 ]

Since the previous setup always sets the PLL using crystal 26MHz, this
doesn't always happen in every MediaTek platform. So the patch added
flexibility for assigning extra member for determining the PLL source
clock.

Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 9f24fcfa304f9c975b63af33e6597722a403afbd..e425e50173c5ac1eeff3e430916ba0dfc0f9b0ce 100644 (file)
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -185,6 +185,7 @@ struct mtk_pll_data {
        uint32_t pcw_reg;
        int pcw_shift;
        const struct mtk_pll_div_table *div_table;
+       const char *parent_name;
 };
 
 void mtk_clk_register_plls(struct device_node *node,

diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 0c2deac17ce958fd415bf80a67944b12b5ca39c1..1502384a30938ef0f501549770aeece66b8dcd56 100644 (file)
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -302,7 +302,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
 
        init.name = data->name;
        init.ops = &mtk_pll_ops;
-       init.parent_names = &parent_name;
+       if (data->parent_name)
+               init.parent_names = &data->parent_name;
+       else
+               init.parent_names = &parent_name;
        init.num_parents = 1;
 
        clk = clk_register(NULL, &pll->hw);