Invalidate d-cache when flash erased

Change-Id: I519f56401ae04d7fa7ccadd143e26a9977ce9d62

diff --git a/os/arch/arm/src/s5j/s5j_qspi.c b/os/arch/arm/src/s5j/s5j_qspi.c
index 60155e3..8212882 100644 (file)
--- a/os/arch/arm/src/s5j/s5j_qspi.c
+++ b/os/arch/arm/src/s5j/s5j_qspi.c
@@ -418,19 +418,27 @@ void QSPI_Sector_Erase(u32 targetAddr)
        Outp32(rERASE_ADDRESS, targetAddr);
 
        Outp8(rSE, QSPI_DUMMY_DATA);
+
+       arch_invalidate_dcache(targetAddr + CONFIG_S5J_FLASH_BASE, (targetAddr + CONFIG_S5J_FLASH_BASE + QSPI_SIZE_4KB));
 }
 
 void QSPI_Block_Erase(u32 targetAddr, eQSPI_BLOCK_SIZE unit)
 {
+       u32 blockEraseSize = 0;
+
        if (unit == BLOCK_64KB) {
                SetBits(rCOMMAND2, 16, 0xFF, COMMAND_ERASE_64KB);
+               blockEraseSize = QSPI_SIZE_64KB;
        } else {
                SetBits(rCOMMAND2, 16, 0xFF, COMMAND_ERASE_32KB);
+               blockEraseSize = QSPI_SIZE_32KB;
        }
 
        Outp32(rERASE_ADDRESS, targetAddr);
 
        Outp8(rBE, QSPI_DUMMY_DATA);
+
+       arch_invalidate_dcache(targetAddr + CONFIG_S5J_FLASH_BASE, (targetAddr + CONFIG_S5J_FLASH_BASE + blockEraseSize));
 }
 
 void QSPI_Chip_Erase(void)

diff --git a/os/arch/arm/src/s5j/s5j_sflash.c b/os/arch/arm/src/s5j/s5j_sflash.c
index 9532e31..d8bae53 100644 (file)
--- a/os/arch/arm/src/s5j/s5j_sflash.c
+++ b/os/arch/arm/src/s5j/s5j_sflash.c
@@ -269,6 +269,7 @@ int s5j_sflash_erase(struct s5j_sflash_dev_s *dev, uint8_t cmd, uint32_t addr)
 {
        int ret;
        uint32_t val;
+       int size = 0;
 
 #ifdef S5J_SFLASH_USE_DIRECT_RW
        /* debug code */
@@ -299,8 +300,10 @@ int s5j_sflash_erase(struct s5j_sflash_dev_s *dev, uint8_t cmd, uint32_t addr)
        case SFLASH_SECTOR_ERASE:
                Outp32(rERASE_ADDRESS, addr);
                Outp8(rSE, QSPI_DUMMY_DATA);
+               size = 4096; /* Sub-sector size */
                break;
        case SFLASH_BLOCK_ERASE_LARGE:
+               size = 65536; /* block size */
                SetBits(rCOMMAND2, 16, 0xFF, COMMAND_ERASE_64KB);
                /* SetBits(rCOMMAND2, 16, 0xFF, COMMAND_ERASE_32KB); */
 
@@ -312,8 +315,10 @@ int s5j_sflash_erase(struct s5j_sflash_dev_s *dev, uint8_t cmd, uint32_t addr)
                break;
        }
 
-       while (getreg32(rRDSR) & 0x1) {
-               usleep(10);
+       while (getreg8(rRDSR) & 0x1) ;
+
+       if (cmd != SFLASH_CHIP_ERASE1) {
+               arch_invalidate_dcache(addr + S5J_SFLASH_MAPPED_ADDR, (addr + S5J_SFLASH_MAPPED_ADDR + size));
        }
 
        return OK;
@@ -405,6 +410,9 @@ int s5j_sflash_write(struct s5j_sflash_dev_s *dev, uint32_t addr, uint8_t *buf,
                addr += readsize;
                i += readsize;
                size -= readsize;
+
+               /* check write in progress */
+               while (getreg8(rRDSR) & 0x1) ;
        }
 
        return OK;