ARM: DRA7: emif: Fix disabling/enabling of refreshes
authorLokesh Vutla <lokeshvutla@ti.com>
Fri, 28 Aug 2015 06:58:25 +0000 (12:28 +0530)
committerTom Rini <trini@konsulko.com>
Fri, 11 Sep 2015 18:05:36 +0000 (14:05 -0400)
clrsetbits_le32/clrbits_le32 takes mask of the bits as input that
are needed to be set/clear. But emif driver passes the shift of the bits.
Fixing it here.

Reported-by: Mark Mckeown <m-mckeown@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arch/arm/cpu/armv7/omap-common/emif-common.c

index f5b22f6..bf7bf26 100644 (file)
@@ -294,8 +294,8 @@ static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
                        EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
 
        /* Disable refreshed before leveling */
-       clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT,
-                       EMIF_REG_INITREF_DIS_SHIFT);
+       clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK,
+                       EMIF_REG_INITREF_DIS_MASK);
 
        /* Start Full leveling */
        writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
@@ -309,7 +309,7 @@ static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
        }
 
        /* Enable refreshes after leveling */
-       clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT);
+       clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 
        debug("HW leveling success\n");
        /*