watchdog: sama5d4_wdt: cleanup the bit definitions

Cleanup the macro definitions to use BIT and align with two spaces.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/1573806579-7981-1-git-send-email-eugen.hristev@microchip.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>

diff --git a/drivers/watchdog/at91sam9_wdt.h b/drivers/watchdog/at91sam9_wdt.h
index 390941c..abfe34d 100644 (file)
--- a/drivers/watchdog/at91sam9_wdt.h
+++ b/drivers/watchdog/at91sam9_wdt.h
@@ -4,33 +4,37 @@
  *
  * Copyright (C) 2007 Andrew Victor
  * Copyright (C) 2007 Atmel Corporation.
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
  *
  * Watchdog Timer (WDT) - System peripherals regsters.
  * Based on AT91SAM9261 datasheet revision D.
+ * Based on SAM9X60 datasheet.
  *
  */
 
 #ifndef AT91_WDT_H
 #define AT91_WDT_H
 
+#include <linux/bits.h>
+
 #define AT91_WDT_CR            0x00                    /* Watchdog Control Register */
-#define                AT91_WDT_WDRSTT         (1    << 0)             /* Restart */
-#define                AT91_WDT_KEY            (0xa5 << 24)            /* KEY Password */
+#define  AT91_WDT_WDRSTT       BIT(0)                  /* Restart */
+#define  AT91_WDT_KEY          (0xa5UL << 24)          /* KEY Password */
 
 #define AT91_WDT_MR            0x04                    /* Watchdog Mode Register */
-#define                AT91_WDT_WDV            (0xfff << 0)            /* Counter Value */
-#define                        AT91_WDT_SET_WDV(x)     ((x) & AT91_WDT_WDV)
-#define                AT91_WDT_WDFIEN         (1     << 12)           /* Fault Interrupt Enable */
-#define                AT91_WDT_WDRSTEN        (1     << 13)           /* Reset Processor */
-#define                AT91_WDT_WDRPROC        (1     << 14)           /* Timer Restart */
-#define                AT91_WDT_WDDIS          (1     << 15)           /* Watchdog Disable */
-#define                AT91_WDT_WDD            (0xfff << 16)           /* Delta Value */
-#define                        AT91_WDT_SET_WDD(x)     (((x) << 16) & AT91_WDT_WDD)
-#define                AT91_WDT_WDDBGHLT       (1     << 28)           /* Debug Halt */
-#define                AT91_WDT_WDIDLEHLT      (1     << 29)           /* Idle Halt */
+#define  AT91_WDT_WDV          (0xfffUL << 0)          /* Counter Value */
+#define  AT91_WDT_SET_WDV(x)   ((x) & AT91_WDT_WDV)
+#define  AT91_WDT_WDFIEN       BIT(12)         /* Fault Interrupt Enable */
+#define  AT91_WDT_WDRSTEN      BIT(13)         /* Reset Processor */
+#define  AT91_WDT_WDRPROC      BIT(14)         /* Timer Restart */
+#define  AT91_WDT_WDDIS                BIT(15)         /* Watchdog Disable */
+#define  AT91_WDT_WDD          (0xfffUL << 16)         /* Delta Value */
+#define  AT91_WDT_SET_WDD(x)   (((x) << 16) & AT91_WDT_WDD)
+#define  AT91_WDT_WDDBGHLT     BIT(28)         /* Debug Halt */
+#define  AT91_WDT_WDIDLEHLT    BIT(29)         /* Idle Halt */
 
-#define AT91_WDT_SR            0x08                    /* Watchdog Status Register */
-#define                AT91_WDT_WDUNF          (1 << 0)                /* Watchdog Underflow */
-#define                AT91_WDT_WDERR          (1 << 1)                /* Watchdog Error */
+#define AT91_WDT_SR            0x08            /* Watchdog Status Register */
+#define  AT91_WDT_WDUNF                BIT(0)          /* Watchdog Underflow */
+#define  AT91_WDT_WDERR                BIT(1)          /* Watchdog Error */
 
 #endif