[ARM][SchedModels] Convert IsLdrAm3NegRegOffPred to MCSchedPredicate

Differential revision: https://reviews.llvm.org/D90045

diff --git a/llvm/include/llvm/Target/TargetInstrPredicate.td b/llvm/include/llvm/Target/TargetInstrPredicate.td
index 91555eb..5c5619e 100644 (file)
--- a/llvm/include/llvm/Target/TargetInstrPredicate.td
+++ b/llvm/include/llvm/Target/TargetInstrPredicate.td
@@ -126,6 +126,11 @@ class CheckRegOperand<int Index, Register R> : CheckOperandBase<Index> {
 // Check if register operand at index `Index` is the invalid register.
 class CheckInvalidRegOperand<int Index> : CheckOperandBase<Index>;
 
+// Return true if machine operand at position `Index` is a valid
+// register operand.
+class CheckValidRegOperand<int Index> :
+  CheckNot<CheckInvalidRegOperand<Index>>;
+
 // Check that the operand at position `Index` is immediate `Imm`.
 // If field `FunctionMapper` is a non-empty string, then function
 // `FunctionMapper` is applied to the operand value, and the return value is then

diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 0b9b076..e6bb5f3 100644 (file)
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -620,20 +620,6 @@ bool ARMBaseInstrInfo::isCPSRDefined(const MachineInstr &MI) {
   return false;
 }
 
-// Load with negative register offset requires additional 1cyc and +I unit
-// for Cortex A57
-bool ARMBaseInstrInfo::isAddrMode3OpMinusReg(const MachineInstr &MI,
-                                             unsigned Op) const {
-  const MachineOperand &Offset = MI.getOperand(Op + 1);
-  const MachineOperand &Opc = MI.getOperand(Op + 2);
-  assert(Opc.isImm());
-  assert(Offset.isReg());
-  int64_t OpcImm = Opc.getImm();
-
-  bool isSub = ARM_AM::getAM3Op(OpcImm) == ARM_AM::sub;
-  return (isSub && Offset.getReg() != 0);
-}
-
 // Load, scaled register offset, not plus LSL2
 bool ARMBaseInstrInfo::isLdstScaledRegNotPlusLsl2(const MachineInstr &MI,
                                                   unsigned Op) const {

diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 26b6d19..50406ad 100644 (file)
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -178,7 +178,6 @@ public:
 
   // CPSR defined in instruction
   static bool isCPSRDefined(const MachineInstr &MI);
-  bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const;
 
   // Load, scaled register offset, not plus LSL2
   bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;

diff --git a/llvm/lib/Target/ARM/ARMSchedule.td b/llvm/lib/Target/ARM/ARMSchedule.td
index 2598d36..c937556 100644 (file)
--- a/llvm/lib/Target/ARM/ARMSchedule.td
+++ b/llvm/lib/Target/ARM/ARMSchedule.td
@@ -171,6 +171,10 @@ let FunctionMapper = "ARM_AM::getAM2ShiftOpc" in {
 def IsLDMBaseRegInList : CheckFunctionPredicate<
   "ARM_MC::isLDMBaseRegInList", "ARM_MC::isLDMBaseRegInList"
 >;
+
+let FunctionMapper = "ARM_AM::getAM3Op" in {
+  class CheckAM3OpSub<int n> : CheckImmOperand_s<n, "ARM_AM::sub"> {}
+}
 //===----------------------------------------------------------------------===//
 // Instruction Itinerary classes used for ARM
 //

diff --git a/llvm/lib/Target/ARM/ARMScheduleA57.td b/llvm/lib/Target/ARM/ARMScheduleA57.td
index bca992f..ce246e8 100644 (file)
--- a/llvm/lib/Target/ARM/ARMScheduleA57.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA57.td
@@ -33,13 +33,13 @@ def IsLdrAm3RegOffPredX2 : MCSchedPredicate<CheckInvalidRegOperand<3>>;
 def IsLdrAm3RegOffPredX3 : MCSchedPredicate<CheckInvalidRegOperand<4>>;
 
 // If Addrmode3 contains "minus register"
-def IsLdrAm3NegRegOffPred :
-  SchedPredicate<[{TII->isAddrMode3OpMinusReg(*MI, 1)}]>;
-// The same predicate with operand offset 2 and 3:
-def IsLdrAm3NegRegOffPredX2 :
-  SchedPredicate<[{TII->isAddrMode3OpMinusReg(*MI, 2)}]>;
-def IsLdrAm3NegRegOffPredX3 :
-  SchedPredicate<[{TII->isAddrMode3OpMinusReg(*MI, 3)}]>;
+class Am3NegativeRegOffset<int n> : MCSchedPredicate<CheckAll<[
+                                      CheckValidRegOperand<n>,
+                                      CheckAM3OpSub<!add(n, 1)>]>>;
+
+def IsLdrAm3NegRegOffPred : Am3NegativeRegOffset<2>;
+def IsLdrAm3NegRegOffPredX2 : Am3NegativeRegOffset<3>;
+def IsLdrAm3NegRegOffPredX3 : Am3NegativeRegOffset<4>;
 
 // Load, scaled register offset, not plus LSL2
 def IsLdstsoScaledNotOptimalPredX0 :

diff --git a/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s b/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
index 318255c..8dc7cfe 100644 (file)
--- a/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
+++ b/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
@@ -202,7 +202,7 @@
 # CHECK-NEXT:  2      4     1.00    *                   ldrbt  r1, [r2], -r6, lsl #12
 # CHECK-NEXT:  2      4     2.00    *                   ldrd   r0, r1, [r5]
 # CHECK-NEXT:  2      4     2.00    *                   ldrd   r0, r1, [r5, r2]
-# CHECK-NEXT:  2      4     2.00    *                   ldrd   r0, r1, [r5, -r2]
+# CHECK-NEXT:  4      5     2.00    *                   ldrd   r0, r1, [r5, -r2]
 # CHECK-NEXT:  2      4     2.00    *                   ldrd   r8, r9, [r2, #15]
 # CHECK-NEXT:  4      5     2.00    *                   ldrd   r2, r3, [r9, #32]!
 # CHECK-NEXT:  4      4     2.00    *                   ldrd   r6, r7, [r1], #8
@@ -218,7 +218,7 @@
 # CHECK-NEXT:  1      4     1.00    *                   ldrh   r1, [r8, #64]!
 # CHECK-NEXT:  2      4     1.00    *                   ldrh   r12, [sp], #4
 # CHECK-NEXT:  1      4     1.00    *                   ldrh   r6, [r5, r4]
-# CHECK-NEXT:  1      4     1.00    *                   ldrh   r6, [r5, -r4]
+# CHECK-NEXT:  2      5     1.00    *                   ldrh   r6, [r5, -r4]
 # CHECK-NEXT:  1      4     1.00    *                   ldrh   r3, [r8, r11]!
 # CHECK-NEXT:  1      4     1.00    *                   ldrh   r1, [r2, -r1]!
 # CHECK-NEXT:  2      4     1.00    *                   ldrh   r9, [r7], r2
@@ -299,7 +299,7 @@
 # CHECK-NEXT:  1      1     1.00           *            strd   r0, r1, [r4]
 # CHECK-NEXT:  1      1     1.00           *            strd   r2, r3, [r6, #1]
 # CHECK-NEXT:  1      1     1.00           *            strd   r2, r3, [r6, r2]
-# CHECK-NEXT:  1      1     1.00           *            strd   r2, r3, [r6, -r2]
+# CHECK-NEXT:  2      3     1.00           *            strd   r2, r3, [r6, -r2]
 # CHECK-NEXT:  2      1     1.00           *            strd   r2, r3, [r7, #22]!
 # CHECK-NEXT:  2      1     1.00           *            strd   r4, r5, [r8], #7
 # CHECK-NEXT:  2      1     1.00           *            strd   r4, r5, [sp], #0
@@ -335,7 +335,7 @@
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]
-# CHECK-NEXT:  -     63.00  63.00  167.00 9.00   57.00   -      -
+# CHECK-NEXT:  -     65.00  65.00  167.00 9.00   57.00   -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]    Instructions:
@@ -374,7 +374,7 @@
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrbt    r1, [r2], -r6, lsl #12
 # CHECK-NEXT:  -      -      -     2.00    -      -      -      -     ldrd     r0, r1, [r5]
 # CHECK-NEXT:  -      -      -     2.00    -      -      -      -     ldrd     r0, r1, [r5, r2]
-# CHECK-NEXT:  -      -      -     2.00    -      -      -      -     ldrd     r0, r1, [r5, -r2]
+# CHECK-NEXT:  -     1.00   1.00   2.00    -      -      -      -     ldrd     r0, r1, [r5, -r2]
 # CHECK-NEXT:  -      -      -     2.00    -      -      -      -     ldrd     r8, r9, [r2, #15]
 # CHECK-NEXT:  -     1.00   1.00   2.00    -      -      -      -     ldrd     r2, r3, [r9, #32]!
 # CHECK-NEXT:  -     1.00   1.00   2.00    -      -      -      -     ldrd     r6, r7, [r1], #8
@@ -390,7 +390,7 @@
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldrh     r1, [r8, #64]!
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrh     r12, [sp], #4
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldrh     r6, [r5, r4]
-# CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldrh     r6, [r5, -r4]
+# CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrh     r6, [r5, -r4]
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldrh     r3, [r8, r11]!
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldrh     r1, [r2, -r1]!
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldrh     r9, [r7], r2
@@ -471,7 +471,7 @@
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -     strd     r0, r1, [r4]
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -     strd     r2, r3, [r6, #1]
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -     strd     r2, r3, [r6, r2]
-# CHECK-NEXT:  -      -      -      -      -     1.00    -      -     strd     r2, r3, [r6, -r2]
+# CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     strd     r2, r3, [r6, -r2]
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     strd     r2, r3, [r7, #22]!
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     strd     r4, r5, [r8], #7
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     strd     r4, r5, [sp], #0