clk: qcom: gcc-msm8939: Add missing system_mm_noc_bfdcd_clk_src

[ Upstream commit dd363e2f7196278e7a30f509a0e8a841cb763b14 ]

The msm8939 has an additional higher operating point for the multi-media
peripherals. The higher throughput MM componets operate off of the
system-mm noc not the system noc.

system_mm_noc_bfdcd_clk_src is the source clock for the higher frequency
capable system noc mm.

Maximum frequency for the MM SNOC is 400 MHz.

Fixes: 1664014e4679 ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220504163835.40130-4-bryan.odonoghue@linaro.org
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c
index 3156865..12bab90 100644 (file)
--- a/drivers/clk/qcom/gcc-msm8939.c
+++ b/drivers/clk/qcom/gcc-msm8939.c
@@ -644,6 +644,18 @@ static struct clk_rcg2 bimc_ddr_clk_src = {
        },
 };
 
+static struct clk_rcg2 system_mm_noc_bfdcd_clk_src = {
+       .cmd_rcgr = 0x2600c,
+       .hid_width = 5,
+       .parent_map = gcc_xo_gpll0_gpll6a_map,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "system_mm_noc_bfdcd_clk_src",
+               .parent_data = gcc_xo_gpll0_gpll6a_parent_data,
+               .num_parents = 3,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
 static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
        F(40000000, P_GPLL0, 10, 1, 2),
        F(80000000, P_GPLL0, 10, 0, 0),
@@ -3623,6 +3635,7 @@ static struct clk_regmap *gcc_msm8939_clocks[] = {
        [GPLL2_VOTE] = &gpll2_vote,
        [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
        [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
+       [SYSTEM_MM_NOC_BFDCD_CLK_SRC] = &system_mm_noc_bfdcd_clk_src.clkr,
        [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
        [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
        [CSI0_CLK_SRC] = &csi0_clk_src.clkr,