[PATCH] Update esd cpci5200 files

Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com>

diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
index dbed597..36bb7ce 100644 (file)
--- a/board/esd/cpci750/cpci750.c
+++ b/board/esd/cpci750/cpci750.c
@@ -29,6 +29,7 @@
  */
 
 #include <common.h>
+#include <command.h>
 #include <74xx_7xx.h>
 #include "../../Marvell/include/memory.h"
 #include "../../Marvell/include/pci.h"
@@ -899,3 +900,24 @@ void board_prebootm_init ()
        flush_data_cache ();
        dcache_disable ();
 }
+
+
+int do_show_cfg(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+       unsigned int reset_sample_low;
+       unsigned int reset_sample_high;
+
+       GT_REG_READ(0x3c4, &reset_sample_low);
+       GT_REG_READ(0x3d4, &reset_sample_high);
+       printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
+
+        return(0);
+}
+
+
+U_BOOT_CMD(
+       show_cfg,       1,      1,      do_show_cfg,
+       "show_cfg- Show Marvell strapping register\n",
+       "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n"
+       );
+

diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c
index 6bdfc1d..c094755 100644 (file)
--- a/board/esd/cpci750/sdram_init.c
+++ b/board/esd/cpci750/sdram_init.c
@@ -1504,6 +1504,8 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
 
 /*     for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
        {
+               int l, l1;
+
                i = info->slot;
                DP (printf
                    ("\n*** Running a MRS cycle for bank %d ***\n", i));
@@ -1511,20 +1513,39 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
                /* map the bank */
                memory_map_bank (i, 0, GB / 4);
 #if 1                          /* test only */
-               /* set SDRAM mode */ /* To_do check it */
+
+               tmp = GTREGREAD (SDRAM_MODE);
+               GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0);
+               GT_REG_WRITE (SDRAM_OPERATION, 0x4);
+               while (GTREGREAD (SDRAM_OPERATION) != 0) {
+                       DP (printf
+                           ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+               }
+
+               GT_REG_WRITE (SDRAM_MODE, tmp | 0x80);
                GT_REG_WRITE (SDRAM_OPERATION, 0x3);
-               check = GTREGREAD (SDRAM_OPERATION);
-               DP (printf
-                   ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
-                    check));
+               while (GTREGREAD (SDRAM_OPERATION) != 0) {
+                       DP (printf
+                           ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+               }
+               l1 = 0;
+               for (l=0;l<200;l++)
+                       l1 += GTREGREAD (SDRAM_OPERATION);
 
+               GT_REG_WRITE (SDRAM_MODE, tmp);
+               GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+               while (GTREGREAD (SDRAM_OPERATION) != 0) {
+                       DP (printf
+                           ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+               }
 
                /* switch back to normal operation mode */
-               GT_REG_WRITE (SDRAM_OPERATION, 0);
-               check = GTREGREAD (SDRAM_OPERATION);
-               DP (printf
-                   ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
-                    check));
+               GT_REG_WRITE (SDRAM_OPERATION, 0x5);
+               while (GTREGREAD (SDRAM_OPERATION) != 0) {
+                       DP (printf
+                           ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+               }
+
 #endif /* test only */
                /* unmap the bank */
                memory_map_bank (i, 0, 0);