drm/amdgpu/gmc10: don't touch gfxhub registers during S0ix

gfxhub registers are part of gfx IP and should not need to be
changed.  Doing so without disabling gfxoff can hang the gfx IP.

v2: add comments explaining why we can skip the interrupt
    control for S0i3

Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 21e4681..8084888 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -78,13 +78,25 @@ gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
                /* MM HUB */
                amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false);
                /* GFX HUB */
-               amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
+               /* This works because this interrupt is only
+                * enabled at init/resume and disabled in
+                * fini/suspend, so the overall state doesn't
+                * change over the course of suspend/resume.
+                */
+               if (!adev->in_s0ix)
+                       amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
                break;
        case AMDGPU_IRQ_STATE_ENABLE:
                /* MM HUB */
                amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true);
                /* GFX HUB */
-               amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
+               /* This works because this interrupt is only
+                * enabled at init/resume and disabled in
+                * fini/suspend, so the overall state doesn't
+                * change over the course of suspend/resume.
+                */
+               if (!adev->in_s0ix)
+                       amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
                break;
        default:
                break;
@@ -1061,9 +1073,12 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
        }
 
        amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
-       r = adev->gfxhub.funcs->gart_enable(adev);
-       if (r)
-               return r;
+
+       if (!adev->in_s0ix) {
+               r = adev->gfxhub.funcs->gart_enable(adev);
+               if (r)
+                       return r;
+       }
 
        r = adev->mmhub.funcs->gart_enable(adev);
        if (r)
@@ -1077,10 +1092,12 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
        value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
                false : true;
 
-       adev->gfxhub.funcs->set_fault_enable_default(adev, value);
+       if (!adev->in_s0ix)
+               adev->gfxhub.funcs->set_fault_enable_default(adev, value);
        adev->mmhub.funcs->set_fault_enable_default(adev, value);
        gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
-       gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
+       if (!adev->in_s0ix)
+               gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
 
        DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
                 (unsigned)(adev->gmc.gart_size >> 20),
@@ -1101,7 +1118,7 @@ static int gmc_v10_0_hw_init(void *handle)
         * harvestable groups in gc_utcl2 need to be programmed before any GFX block
         * register setup within GMC, or else system hang when harvesting SA.
         */
-       if (adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest)
+       if (!adev->in_s0ix && adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest)
                adev->gfxhub.funcs->utcl2_harvest(adev);
 
        r = gmc_v10_0_gart_enable(adev);
@@ -1129,7 +1146,8 @@ static int gmc_v10_0_hw_init(void *handle)
  */
 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
 {
-       adev->gfxhub.funcs->gart_disable(adev);
+       if (!adev->in_s0ix)
+               adev->gfxhub.funcs->gart_disable(adev);
        adev->mmhub.funcs->gart_disable(adev);
 }