.hsync_len = 64,
.hfront_porch = 12,
.hback_porch = 68,
- .vsw = 5,
+ .vsync_len = 5,
.vfp = 5,
.vbp = 41,
.hback_porch = 80,
.vfp = 3,
- .vsw = 4,
+ .vsync_len = 4,
.vbp = 7,
.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
.hsync_len = 96,
.hfront_porch = 16,
.hback_porch = 48,
- .vsw = 2,
+ .vsync_len = 2,
.vfp = 11,
.vbp = 31,
.hfront_porch = 20,
.hback_porch = 68,
- .vsw = 2,
+ .vsync_len = 2,
.vfp = 4,
.vbp = 18,
.hsync_len = 1,
.hback_porch = 4,
.vfp = 3,
- .vsw = 1,
+ .vsync_len = 1,
.vbp = 4,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.hfront_porch = 1,
.hback_porch = 28,
- .vsw = 1,
+ .vsync_len = 1,
.vfp = 1,
.vbp = 1,
.hsync_len = 4,
.hback_porch = 24,
.vfp = 3,
- .vsw = 3,
+ .vsync_len = 3,
.vbp = 4,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.hsync_len = 8,
.hback_porch = 8,
.vfp = 4,
- .vsw = 2,
+ .vsync_len = 2,
.vbp = 2,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.hfront_porch = 68,
.hback_porch = 214,
- .vsw = 1,
+ .vsync_len = 1,
.vfp = 39,
.vbp = 34,
} else {
int wbdelay;
- wbdelay = min(mgr_timings->vfp + mgr_timings->vsw +
+ wbdelay = min(mgr_timings->vfp + mgr_timings->vsync_len +
mgr_timings->vbp, 255);
/* WBDELAYCOUNT */
if (!_dispc_lcd_timings_ok(timings->hsync_len,
timings->hfront_porch, timings->hback_porch,
- timings->vsw, timings->vfp, timings->vbp))
+ timings->vsync_len, timings->vfp, timings->vbp))
return false;
}
if (dss_mgr_is_lcd(channel)) {
_dispc_mgr_set_lcd_timings(channel, t.hsync_len, t.hfront_porch,
- t.hback_porch, t.vsw, t.vfp, t.vbp,
+ t.hback_porch, t.vsync_len, t.vfp, t.vbp,
t.vsync_level, t.hsync_level, t.data_pclk_edge,
t.de_level, t.sync_pclk_edge);
xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch;
- ytot = t.vactive + t.vfp + t.vsw + t.vbp;
+ ytot = t.vactive + t.vfp + t.vsync_len + t.vbp;
ht = timings->pixelclock / xtot;
vt = timings->pixelclock / xtot / ytot;
DSSDBG("pck %u\n", timings->pixelclock);
DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
t.hsync_len, t.hfront_porch, t.hback_porch,
- t.vsw, t.vfp, t.vbp);
+ t.vsync_len, t.vfp, t.vbp);
DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
t.vsync_level, t.hsync_level, t.data_pclk_edge,
t.de_level, t.sync_pclk_edge);
.hactive = 8, .vactive = 1,
.pixelclock = 16000000,
.hsync_len = 8, .hfront_porch = 4, .hback_porch = 4,
- .vsw = 1, .vfp = 1, .vbp = 1,
+ .vsync_len = 1, .vfp = 1, .vbp = 1,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.interlace = false,
ovt->vactive = vm->vactive;
ovt->vbp = vm->vback_porch;
ovt->vfp = vm->vfront_porch;
- ovt->vsw = vm->vsync_len;
+ ovt->vsync_len = vm->vsync_len;
ovt->vsync_level = vm->flags & DISPLAY_FLAGS_VSYNC_HIGH ?
OMAPDSS_SIG_ACTIVE_HIGH :
vm->vactive = ovt->vactive;
vm->vback_porch = ovt->vbp;
vm->vfront_porch = ovt->vfp;
- vm->vsync_len = ovt->vsw;
+ vm->vsync_len = ovt->vsync_len;
if (ovt->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH)
vm->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
t->pixelclock = pck;
t->hactive = ctx->config->timings->hactive;
t->vactive = ctx->config->timings->vactive;
- t->hsync_len = t->hfront_porch = t->hback_porch = t->vsw = 1;
+ t->hsync_len = t->hfront_porch = t->hback_porch = t->vsync_len = 1;
t->vfp = t->vbp = 0;
return true;
dsi_vm->hact = xres;
dsi_vm->hfp = hfp;
- dsi_vm->vsa = req_vm->vsw;
+ dsi_vm->vsa = req_vm->vsync_len;
dsi_vm->vbp = req_vm->vbp;
dsi_vm->vact = req_vm->vactive;
dsi_vm->vfp = req_vm->vfp;
video_cfg->hblank = cfg->timings.hfront_porch +
cfg->timings.hback_porch + cfg->timings.hsync_len;
video_cfg->vblank_osc = 0;
- video_cfg->vblank = cfg->timings.vsw +
+ video_cfg->vblank = cfg->timings.vsync_len +
cfg->timings.vfp + cfg->timings.vbp;
video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode;
video_cfg->v_fc_config.timings.vactive /= 2;
video_cfg->vblank /= 2;
video_cfg->v_fc_config.timings.vfp /= 2;
- video_cfg->v_fc_config.timings.vsw /= 2;
+ video_cfg->v_fc_config.timings.vsync_len /= 2;
video_cfg->v_fc_config.timings.vbp /= 2;
}
/* set vertical sync pulse width */
REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH,
- cfg->v_fc_config.timings.vsw, 5, 0);
+ cfg->v_fc_config.timings.vsync_len, 5, 0);
/* select DVI mode */
REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF,
timing_v |= FLD_VAL(timings->vbp, 31, 20);
timing_v |= FLD_VAL(timings->vfp, 19, 8);
- timing_v |= FLD_VAL(timings->vsw, 7, 0);
+ timing_v |= FLD_VAL(timings->vsync_len, 7, 0);
hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);
}
timings->hsync_len = param->timings.hsync_len;
timings->vbp = param->timings.vbp;
timings->vfp = param->timings.vfp;
- timings->vsw = param->timings.vsw;
+ timings->vsync_len = param->timings.vsync_len;
timings->vsync_level = param->timings.vsync_level;
timings->hsync_level = param->timings.hsync_level;
video_fmt->y_res /= 2;
timings->vbp /= 2;
timings->vfp /= 2;
- timings->vsw /= 2;
+ timings->vsync_len /= 2;
}
if (param->timings.double_pixel) {
/* Unit: pixel clocks */
u16 hback_porch; /* Horizontal back porch */
/* Unit: line clocks */
- u16 vsw; /* Vertical synchronization pulse width */
+ u16 vsync_len; /* Vertical synchronization pulse width */
/* Unit: line clocks */
u16 vfp; /* Vertical front porch */
/* Unit: line clocks */
rfbi.timings.hsync_len = 1;
rfbi.timings.hfront_porch = 1;
rfbi.timings.hback_porch = 1;
- rfbi.timings.vsw = 1;
+ rfbi.timings.vsync_len = 1;
rfbi.timings.vfp = 0;
rfbi.timings.vbp = 0;
.hsync_len = 64,
.hfront_porch = 12,
.hback_porch = 68,
- .vsw = 5,
+ .vsync_len = 5,
.vfp = 5,
.vbp = 41,
.hsync_len = 64,
.hfront_porch = 16,
.hback_porch = 58,
- .vsw = 6,
+ .vsync_len = 6,
.vfp = 6,
.vbp = 31,
mode->vdisplay = timings->vactive;
mode->vsync_start = mode->vdisplay + timings->vfp;
- mode->vsync_end = mode->vsync_start + timings->vsw;
+ mode->vsync_end = mode->vsync_start + timings->vsync_len;
mode->vtotal = mode->vsync_end + timings->vbp;
mode->flags = 0;
timings->vactive = mode->vdisplay;
timings->vfp = mode->vsync_start - mode->vdisplay;
- timings->vsw = mode->vsync_end - mode->vsync_start;
+ timings->vsync_len = mode->vsync_end - mode->vsync_start;
timings->vbp = mode->vtotal - mode->vsync_end;
timings->interlace = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);