return -ENODEV;
/*
+ * The ->setup_clock() callback is optional, but if encoders don't
+ * implement it they most likely need to do the equivalent within the
+ * ->mode_fixup() callback.
+ */
+ if (!output->ops || !output->ops->setup_clock)
+ return 0;
+
+ /*
* This assumes that the parent clock is pll_d_out0 or pll_d2_out
* respectively, each of which divides the base pll_d by 2.
*/
- err = tegra_output_setup_clock(output, dc->clk, pclk, &div);
+ err = output->ops->setup_clock(output, dc->clk, pclk, &div);
if (err < 0) {
dev_err(dc->dev, "failed to setup clock: %ld\n", err);
return err;
return output ? -ENOSYS : -EINVAL;
}
-static inline int tegra_output_setup_clock(struct tegra_output *output,
- struct clk *clk, unsigned long pclk,
- unsigned int *div)
-{
- if (output && output->ops && output->ops->setup_clock)
- return output->ops->setup_clock(output, clk, pclk, div);
-
- return output ? -ENOSYS : -EINVAL;
-}
-
static inline int tegra_output_check_mode(struct tegra_output *output,
struct drm_display_mode *mode,
enum drm_mode_status *status)