// Relaxing branches involves creating new basic blocks, so re-eval
// end() for termination.
- for (MachineFunction::iterator I = MF->begin(); I != MF->end(); ++I) {
- MachineBasicBlock &MBB = *I;
-
+ for (MachineBasicBlock &MBB : *MF) {
// Empty block?
MachineBasicBlock::iterator Last = MBB.getLastNonDebugInstr();
if (Last == MBB.end())
assert(Old != New && "Not making a change?");
bool MadeChange = false;
MachineJumpTableEntry &JTE = JumpTables[Idx];
- for (size_t j = 0, e = JTE.MBBs.size(); j != e; ++j)
- if (JTE.MBBs[j] == Old) {
- JTE.MBBs[j] = New;
+ for (MachineBasicBlock *&MBB : JTE.MBBs)
+ if (MBB == Old) {
+ MBB = New;
MadeChange = true;
}
return MadeChange;
for (unsigned i = 0, e = JumpTables.size(); i != e; ++i) {
OS << printJumpTableEntryReference(i) << ':';
- for (unsigned j = 0, f = JumpTables[i].MBBs.size(); j != f; ++j)
- OS << ' ' << printMBBReference(*JumpTables[i].MBBs[j]);
+ for (const MachineBasicBlock *MBB : JumpTables[i].MBBs)
+ OS << ' ' << printMBBReference(*MBB);
if (i != e)
OS << '\n';
}
void HexagonGenInsert::buildOrderingMF(RegisterOrdering &RO) const {
unsigned Index = 0;
- using mf_iterator = MachineFunction::const_iterator;
-
- for (mf_iterator A = MFN->begin(), Z = MFN->end(); A != Z; ++A) {
- const MachineBasicBlock &B = *A;
+ for (const MachineBasicBlock &B : *MFN) {
if (!CMS->BT.reached(&B))
continue;
- using mb_iterator = MachineBasicBlock::const_iterator;
-
- for (mb_iterator I = B.begin(), E = B.end(); I != E; ++I) {
- const MachineInstr *MI = &*I;
- for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
+ for (const MachineInstr &MI : B) {
+ for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
+ const MachineOperand &MO = MI.getOperand(i);
if (MO.isReg() && MO.isDef()) {
Register R = MO.getReg();
assert(MO.getSubReg() == 0 && "Unexpected subregister in definition");
if (TII->analyzeBranch(*ExitingBlock, TB, FB, Tmp1, false))
return nullptr;
- for (MBBVector::iterator I = Preds.begin(), E = Preds.end(); I != E; ++I) {
- MachineBasicBlock *PB = *I;
+ for (MachineBasicBlock *PB : Preds) {
bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp1, false);
if (NotAnalyzed)
return nullptr;
bool Changed = false;
InstrsToRemove.clear();
- for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE;
- ++BI) {
- for (MachineBasicBlock::iterator I = (*BI).begin(), E = (*BI).end();
- I != E; ++I) {
- MachineInstr &MI = *I;
+ for (MachineBasicBlock &MBB : MF)
+ for (MachineInstr &MI : MBB)
Changed |= processInstr(MI);
- }
- }
// Now clean up any handle-access instructions
// This is needed in debug mode when code cleanup passes are not executed,
// but we need the handle access to be eliminated because they are not
// valid instructions when image handles are disabled.
- for (DenseSet<MachineInstr *>::iterator I = InstrsToRemove.begin(),
- E = InstrsToRemove.end(); I != E; ++I) {
- (*I)->eraseFromParent();
- }
+ for (MachineInstr *MI : InstrsToRemove)
+ MI->eraseFromParent();
return Changed;
}
static_cast<const PPCInstrInfo *>(Fn.getSubtarget().getInstrInfo());
unsigned FuncSize = GetInitialOffset(Fn);
- for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
- ++MFI) {
- MachineBasicBlock *MBB = &*MFI;
-
+ for (MachineBasicBlock &MBB : Fn) {
// The end of the previous block may have extra nops if this block has an
// alignment requirement.
- if (MBB->getNumber() > 0) {
- unsigned AlignExtra = GetAlignmentAdjustment(*MBB, FuncSize);
+ if (MBB.getNumber() > 0) {
+ unsigned AlignExtra = GetAlignmentAdjustment(MBB, FuncSize);
- auto &BS = BlockSizes[MBB->getNumber()-1];
+ auto &BS = BlockSizes[MBB.getNumber()-1];
BS.first += AlignExtra;
BS.second = AlignExtra;
unsigned BlockSize = 0;
unsigned UnalignedBytesRemaining = 0;
- for (MachineInstr &MI : *MBB) {
+ for (MachineInstr &MI : MBB) {
unsigned MINumBytes = TII->getInstSizeInBytes(MI);
if (MI.isInlineAsm() && (FirstImpreciseBlock < 0))
- FirstImpreciseBlock = MBB->getNumber();
+ FirstImpreciseBlock = MBB.getNumber();
if (TII->isPrefixed(MI.getOpcode())) {
NumPrefixed++;
BlockSize += MINumBytes;
}
- BlockSizes[MBB->getNumber()].first = BlockSize;
+ BlockSizes[MBB.getNumber()].first = BlockSize;
FuncSize += BlockSize;
}
/// Modify the basic block align adjustment.
void PPCBSel::modifyAdjustment(MachineFunction &Fn) {
unsigned Offset = GetInitialOffset(Fn);
- for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
- ++MFI) {
- MachineBasicBlock *MBB = &*MFI;
-
- if (MBB->getNumber() > 0) {
- auto &BS = BlockSizes[MBB->getNumber()-1];
+ for (MachineBasicBlock &MBB : Fn) {
+ if (MBB.getNumber() > 0) {
+ auto &BS = BlockSizes[MBB.getNumber()-1];
BS.first -= BS.second;
Offset -= BS.second;
- unsigned AlignExtra = GetAlignmentAdjustment(*MBB, Offset);
+ unsigned AlignExtra = GetAlignmentAdjustment(MBB, Offset);
BS.first += AlignExtra;
BS.second = AlignExtra;
Offset += AlignExtra;
}
- Offset += BlockSizes[MBB->getNumber()].first;
+ Offset += BlockSizes[MBB.getNumber()].first;
}
}
// Verify that all bdnz/bdz instructions are dominated by a loop mtctr before
// any other instructions that might clobber the ctr register.
- for (MachineFunction::iterator I = MF.begin(), IE = MF.end();
- I != IE; ++I) {
- MachineBasicBlock *MBB = &*I;
- if (!MDT->isReachableFromEntry(MBB))
+ for (MachineBasicBlock &MBB : MF) {
+ if (!MDT->isReachableFromEntry(&MBB))
continue;
- for (MachineBasicBlock::iterator MII = MBB->getFirstTerminator(),
- MIIE = MBB->end(); MII != MIIE; ++MII) {
+ for (MachineBasicBlock::iterator MII = MBB.getFirstTerminator(),
+ MIIE = MBB.end(); MII != MIIE; ++MII) {
unsigned Opc = MII->getOpcode();
if (Opc == PPC::BDNZ8 || Opc == PPC::BDNZ ||
Opc == PPC::BDZ8 || Opc == PPC::BDZ)
- if (!verifyCTRBranch(MBB, MII))
+ if (!verifyCTRBranch(&MBB, MII))
llvm_unreachable("Invalid PPC CTR loop!");
}
}
bool Changed = false;
TII = static_cast<const PPCInstrInfo *>(MF.getSubtarget().getInstrInfo());
TRI = &TII->getRegisterInfo();
- for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
- MachineBasicBlock &MBB = *I;
+ for (MachineBasicBlock &MBB : MF) {
for (MachineBasicBlock::iterator MBBI = MBB.begin(), MBBE = MBB.end();
MBBI != MBBE;) {
MachineInstr &MI = *MBBI;
unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FP8Reg;
- for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
- BI != BE; ++BI)
- for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
+ for (MachineBasicBlock &MBB : MF)
+ for (MachineBasicBlock::iterator MBBI = MBB.end(); MBBI != MBB.begin();) {
--MBBI;
for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
MachineOperand &MO = MBBI->getOperand(I);
}
static bool MBBDefinesCTR(MachineBasicBlock &MBB) {
- for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
- I != IE; ++I)
- if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
+ for (MachineInstr &MI : MBB)
+ if (MI.definesRegister(PPC::CTR) || MI.definesRegister(PPC::CTR8))
return true;
return false;
}
// instructions to fill delay slot.
F.getRegInfo().invalidateLiveness();
- for (MachineFunction::iterator FI = F.begin(), FE = F.end();
- FI != FE; ++FI)
- Changed |= runOnMachineBasicBlock(*FI);
+ for (MachineBasicBlock &MBB : F)
+ Changed |= runOnMachineBasicBlock(MBB);
return Changed;
}
DebugLoc DL = DebugLoc();
bool Modified = false;
- for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
- MachineBasicBlock &MBB = *MFI;
+ for (MachineBasicBlock &MBB : MF) {
for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
MachineInstr &MI = *MBBI;
unsigned Opcode = MI.getOpcode();
Subtarget = &MF.getSubtarget<SparcSubtarget>();
bool Modified = false;
- for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
- MachineBasicBlock &MBB = *MFI;
- for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
- MachineInstr &MI = *MBBI;
+ for (MachineBasicBlock &MBB : MF) {
+ for (MachineInstr &MI : MBB) {
unsigned Opcode = MI.getOpcode();
if (Opcode == SP::CALL && MI.getNumOperands() > 0) {
MachineOperand &MO = MI.getOperand(0);
DebugLoc DL = DebugLoc();
bool Modified = false;
- for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
- MachineBasicBlock &MBB = *MFI;
+ for (MachineBasicBlock &MBB : MF) {
for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
MachineInstr &MI = *MBBI;
unsigned Opcode = MI.getOpcode();
}
// Rewrite MBB's Live-ins.
- for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
- MBB != E; ++MBB) {
+ for (MachineBasicBlock &MBB : MF) {
for (unsigned reg = SP::I0_I1; reg <= SP::I6_I7; ++reg) {
- if (!MBB->isLiveIn(reg))
+ if (!MBB.isLiveIn(reg))
continue;
- MBB->removeLiveIn(reg);
- MBB->addLiveIn(reg - SP::I0_I1 + SP::O0_O1);
+ MBB.removeLiveIn(reg);
+ MBB.addLiveIn(reg - SP::I0_I1 + SP::O0_O1);
}
for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
- if (!MBB->isLiveIn(reg))
+ if (!MBB.isLiveIn(reg))
continue;
- MBB->removeLiveIn(reg);
- MBB->addLiveIn(reg - SP::I0 + SP::O0);
+ MBB.removeLiveIn(reg);
+ MBB.addLiveIn(reg - SP::I0 + SP::O0);
}
}
const XCoreInstrInfo &TII =
*static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo());
unsigned StackSize = MF.getFrameInfo().getStackSize();
- for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
- ++MFI) {
- MachineBasicBlock &MBB = *MFI;
+ for (MachineBasicBlock &MBB : MF) {
for (MachineBasicBlock::iterator MBBI = MBB.begin(), EE = MBB.end();
MBBI != EE; ++MBBI) {
if (MBBI->getOpcode() == XCore::FRAME_TO_ARGS_OFFSET) {