<&gcc GPLL0_VOTE>,
<&gcc GPLL1_VOTE>,
<&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
- <&dsi0_phy 1>,
- <&dsi0_phy 0>,
- <&dsi1_phy 1>,
- <&dsi1_phy 0>,
+ <&mdss_dsi0_phy 1>,
+ <&mdss_dsi0_phy 0>,
+ <&mdss_dsi1_phy 1>,
+ <&mdss_dsi1_phy 0>,
<0>,
<0>,
<0>;
port@0 {
reg = <0>;
mdp5_intf1_out: endpoint {
- remote-endpoint = <&dsi0_in>;
+ remote-endpoint = <&mdss_dsi0_in>;
};
};
port@1 {
reg = <1>;
mdp5_intf2_out: endpoint {
- remote-endpoint = <&dsi1_in>;
+ remote-endpoint = <&mdss_dsi1_in>;
};
};
};
};
- dsi0: dsi@fd922800 {
+ mdss_dsi0: dsi@fd922800 {
compatible = "qcom,msm8974-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
reg = <0xfd922800 0x1f8>;
interrupts = <4>;
assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
- assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_AHB_CLK>,
"core",
"core_mmss";
- phys = <&dsi0_phy>;
+ phys = <&mdss_dsi0_phy>;
status = "disabled";
port@0 {
reg = <0>;
- dsi0_in: endpoint {
+ mdss_dsi0_in: endpoint {
remote-endpoint = <&mdp5_intf1_out>;
};
};
port@1 {
reg = <1>;
- dsi0_out: endpoint {
+ mdss_dsi0_out: endpoint {
};
};
};
};
- dsi0_phy: phy@fd922a00 {
+ mdss_dsi0_phy: phy@fd922a00 {
compatible = "qcom,dsi-phy-28nm-hpm";
reg = <0xfd922a00 0xd4>,
<0xfd922b00 0x280>,
status = "disabled";
};
- dsi1: dsi@fd922e00 {
+ mdss_dsi1: dsi@fd922e00 {
compatible = "qcom,msm8974-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
reg = <0xfd922e00 0x1f8>;
interrupts = <4>;
assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
- assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
+ assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_AHB_CLK>,
"core",
"core_mmss";
- phys = <&dsi1_phy>;
+ phys = <&mdss_dsi1_phy>;
status = "disabled";
port@0 {
reg = <0>;
- dsi1_in: endpoint {
+ mdss_dsi1_in: endpoint {
remote-endpoint = <&mdp5_intf2_out>;
};
};
port@1 {
reg = <1>;
- dsi1_out: endpoint {
+ mdss_dsi1_out: endpoint {
};
};
};
};
- dsi1_phy: phy@fd923000 {
+ mdss_dsi1_phy: phy@fd923000 {
compatible = "qcom,dsi-phy-28nm-hpm";
reg = <0xfd923000 0xd4>,
<0xfd923100 0x280>,
};
};
-&dsi0 {
+&gpu {
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
status = "okay";
vdda-supply = <&pma8084_l2>;
port {
panel_in: endpoint {
- remote-endpoint = <&dsi0_out>;
+ remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
-&dsi0_out {
+&mdss_dsi0_out {
remote-endpoint = <&panel_in>;
data-lanes = <0 1 2 3>;
};
-&dsi0_phy {
+&mdss_dsi0_phy {
status = "okay";
vddio-supply = <&pma8084_l12>;
};
-&gpu {
- status = "okay";
-};
-
-&mdss {
- status = "okay";
-};
-
&pma8084_gpios {
gpio_keys_pin_a: gpio-keys-active-state {
pins = "gpio2", "gpio3", "gpio5";