Glue = Chain.getValue(1);
}
- if (isa<GlobalAddressSDNode>(Callee)) {
- Callee = lowerGlobalAddress(Callee, DAG);
- } else if (isa<ExternalSymbolSDNode>(Callee)) {
- Callee = lowerExternalSymbol(Callee, DAG);
+ // If the callee is a GlobalAddress/ExternalSymbol node, turn it into a
+ // TargetGlobalAddress/TargetExternalSymbol node so that legalize won't
+ // split it and then direct call can be matched by PseudoCALL.
+ if (GlobalAddressSDNode *S = dyn_cast<GlobalAddressSDNode>(Callee)) {
+ Callee = DAG.getTargetGlobalAddress(S->getGlobal(), DL, PtrVT, 0, 0);
+ } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
+ Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, 0);
}
// The first call operand is the chain and the second is the target address.
case TargetOpcode::KILL:
case TargetOpcode::DBG_VALUE:
return 0;
+ case RISCV::PseudoCALL:
+ return 8;
case TargetOpcode::INLINEASM: {
const MachineFunction &MF = *MI.getParent()->getParent();
const auto &TM = static_cast<const RISCVTargetMachine &>(MF.getTarget());
(PseudoBRIND GPR:$rs1, simm12:$imm12)>;
// PseudoCALL is a pseudo instruction which will eventually expand to auipc
-// and jalr. Define AsmString because we want assembler could print "call"
-// when compile with -S. Define isCodeGenOnly = 0 because we want parser
-// could parsing assembly "call" instruction.
-let isCall = 1, Defs = [X1], isCodeGenOnly = 0,
- hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+// and jalr while encoding. This is desirable, as an auipc+jalr pair with
+// R_RISCV_CALL and R_RISCV_RELAX relocations can be be relaxed by the linker
+// if the offset fits in a signed 21-bit immediate.
+// Define AsmString to print "call" when compile with -S flag.
+// Define isCodeGenOnly = 0 to support parsing assembly "call" instruction.
+let isCall = 1, Defs = [X1], isCodeGenOnly = 0 in
def PseudoCALL : Pseudo<(outs), (ins bare_symbol:$func),
- []> {
+ [(Call tglobaladdr:$func)]> {
let AsmString = "call\t$func";
}
+def : Pat<(Call texternalsym:$func), (PseudoCALL texternalsym:$func)>;
+
let isCall = 1, Defs = [X1] in
def PseudoCALLIndirect : Pseudo<(outs), (ins GPR:$rs1), [(Call GPR:$rs1)]>,
PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
; RV32I-NEXT: andi a0, a0, -16
; RV32I-NEXT: sub a0, sp, a0
; RV32I-NEXT: mv sp, a0
-; RV32I-NEXT: lui a1, %hi(notdead)
-; RV32I-NEXT: addi a1, a1, %lo(notdead)
-; RV32I-NEXT: jalr a1
+; RV32I-NEXT: call notdead
; RV32I-NEXT: addi sp, s0, -16
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: andi a0, a0, -16
; RV32I-NEXT: sub a0, sp, a0
; RV32I-NEXT: mv sp, a0
-; RV32I-NEXT: lui a1, %hi(notdead)
-; RV32I-NEXT: addi a1, a1, %lo(notdead)
-; RV32I-NEXT: jalr a1
+; RV32I-NEXT: call notdead
; RV32I-NEXT: mv sp, s1
; RV32I-NEXT: addi sp, s0, -16
; RV32I-NEXT: lw s1, 4(sp)
; RV32I-NEXT: sw a1, 4(sp)
; RV32I-NEXT: addi a1, zero, 9
; RV32I-NEXT: sw a1, 0(sp)
-; RV32I-NEXT: lui a1, %hi(func)
-; RV32I-NEXT: addi t0, a1, %lo(func)
; RV32I-NEXT: addi a1, zero, 2
; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a5, zero, 6
; RV32I-NEXT: addi a6, zero, 7
; RV32I-NEXT: addi a7, zero, 8
-; RV32I-NEXT: jalr t0
+; RV32I-NEXT: call func
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: addi sp, s0, -16
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: addi a1, zero, 42
; RV32I-NEXT: bne a0, a1, .LBB0_3
; RV32I-NEXT: # %bb.1: # %true
-; RV32I-NEXT: lui a0, %hi(test_true)
-; RV32I-NEXT: addi a0, a0, %lo(test_true)
+; RV32I-NEXT: call test_true
; RV32I-NEXT: .LBB0_2: # %true
-; RV32I-NEXT: jalr a0
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_3: # %false
-; RV32I-NEXT: lui a0, %hi(test_false)
-; RV32I-NEXT: addi a0, a0, %lo(test_false)
+; RV32I-NEXT: call test_false
; RV32I-NEXT: j .LBB0_2
%tst = icmp eq i32 %in, 42
br i1 %tst, label %true, label %false, !prof !0
; RV32I-NEXT: addi a1, zero, 42
; RV32I-NEXT: beq a0, a1, .LBB1_3
; RV32I-NEXT: # %bb.1: # %false
-; RV32I-NEXT: lui a0, %hi(test_false)
-; RV32I-NEXT: addi a0, a0, %lo(test_false)
+; RV32I-NEXT: call test_false
; RV32I-NEXT: .LBB1_2: # %true
-; RV32I-NEXT: jalr a0
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB1_3: # %true
-; RV32I-NEXT: lui a0, %hi(test_true)
-; RV32I-NEXT: addi a0, a0, %lo(test_true)
+; RV32I-NEXT: call test_true
; RV32I-NEXT: j .LBB1_2
%tst = icmp eq i32 %in, 42
br i1 %tst, label %true, label %false, !prof !1
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257
-; RV32I-NEXT: lui a2, %hi(__mulsi3)
-; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
-; RV32I-NEXT: jalr a2
+; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB3_3
; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257
-; RV32I-NEXT: lui a2, %hi(__mulsi3)
-; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
-; RV32I-NEXT: jalr a2
+; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB4_3
; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257
-; RV32I-NEXT: lui a2, %hi(__mulsi3)
-; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
-; RV32I-NEXT: jalr a2
+; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB5_3
; RV32I-NEXT: .LBB5_2:
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257
-; RV32I-NEXT: lui a2, %hi(__mulsi3)
-; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
-; RV32I-NEXT: jalr a2
+; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB6_3
; RV32I-NEXT: .LBB6_2:
define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-LABEL: test_cttz_i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -48
-; RV32I-NEXT: sw ra, 44(sp)
-; RV32I-NEXT: sw s1, 40(sp)
-; RV32I-NEXT: sw s2, 36(sp)
-; RV32I-NEXT: sw s3, 32(sp)
-; RV32I-NEXT: sw s4, 28(sp)
-; RV32I-NEXT: sw s5, 24(sp)
-; RV32I-NEXT: sw s6, 20(sp)
-; RV32I-NEXT: sw s7, 16(sp)
-; RV32I-NEXT: sw s8, 12(sp)
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp)
+; RV32I-NEXT: sw s1, 24(sp)
+; RV32I-NEXT: sw s2, 20(sp)
+; RV32I-NEXT: sw s3, 16(sp)
+; RV32I-NEXT: sw s4, 12(sp)
+; RV32I-NEXT: sw s5, 8(sp)
+; RV32I-NEXT: sw s6, 4(sp)
+; RV32I-NEXT: sw s7, 0(sp)
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s4, a1, 257
-; RV32I-NEXT: lui a1, %hi(__mulsi3)
-; RV32I-NEXT: addi s7, a1, %lo(__mulsi3)
; RV32I-NEXT: lui a1, 61681
-; RV32I-NEXT: addi s8, a1, -241
-; RV32I-NEXT: and a0, a0, s8
+; RV32I-NEXT: addi s7, a1, -241
+; RV32I-NEXT: and a0, a0, s7
; RV32I-NEXT: mv a1, s4
-; RV32I-NEXT: jalr s7
+; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: addi a0, s2, -1
; RV32I-NEXT: not a1, s2
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: and a0, a0, s8
+; RV32I-NEXT: and a0, a0, s7
; RV32I-NEXT: mv a1, s4
-; RV32I-NEXT: jalr s7
+; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: bnez s3, .LBB7_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: srli a0, s1, 24
; RV32I-NEXT: .LBB7_3:
; RV32I-NEXT: mv a1, zero
-; RV32I-NEXT: lw s8, 12(sp)
-; RV32I-NEXT: lw s7, 16(sp)
-; RV32I-NEXT: lw s6, 20(sp)
-; RV32I-NEXT: lw s5, 24(sp)
-; RV32I-NEXT: lw s4, 28(sp)
-; RV32I-NEXT: lw s3, 32(sp)
-; RV32I-NEXT: lw s2, 36(sp)
-; RV32I-NEXT: lw s1, 40(sp)
-; RV32I-NEXT: lw ra, 44(sp)
-; RV32I-NEXT: addi sp, sp, 48
+; RV32I-NEXT: lw s7, 0(sp)
+; RV32I-NEXT: lw s6, 4(sp)
+; RV32I-NEXT: lw s5, 8(sp)
+; RV32I-NEXT: lw s4, 12(sp)
+; RV32I-NEXT: lw s3, 16(sp)
+; RV32I-NEXT: lw s2, 20(sp)
+; RV32I-NEXT: lw s1, 24(sp)
+; RV32I-NEXT: lw ra, 28(sp)
+; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
%tmp = call i64 @llvm.cttz.i64(i64 %a, i1 false)
ret i64 %tmp
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257
-; RV32I-NEXT: lui a2, %hi(__mulsi3)
-; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
-; RV32I-NEXT: jalr a2
+; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257
-; RV32I-NEXT: lui a2, %hi(__mulsi3)
-; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
-; RV32I-NEXT: jalr a2
+; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257
-; RV32I-NEXT: lui a2, %hi(__mulsi3)
-; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
-; RV32I-NEXT: jalr a2
+; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-LABEL: test_cttz_i64_zero_undef:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -48
-; RV32I-NEXT: sw ra, 44(sp)
-; RV32I-NEXT: sw s1, 40(sp)
-; RV32I-NEXT: sw s2, 36(sp)
-; RV32I-NEXT: sw s3, 32(sp)
-; RV32I-NEXT: sw s4, 28(sp)
-; RV32I-NEXT: sw s5, 24(sp)
-; RV32I-NEXT: sw s6, 20(sp)
-; RV32I-NEXT: sw s7, 16(sp)
-; RV32I-NEXT: sw s8, 12(sp)
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp)
+; RV32I-NEXT: sw s1, 24(sp)
+; RV32I-NEXT: sw s2, 20(sp)
+; RV32I-NEXT: sw s3, 16(sp)
+; RV32I-NEXT: sw s4, 12(sp)
+; RV32I-NEXT: sw s5, 8(sp)
+; RV32I-NEXT: sw s6, 4(sp)
+; RV32I-NEXT: sw s7, 0(sp)
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s4, a1, 257
-; RV32I-NEXT: lui a1, %hi(__mulsi3)
-; RV32I-NEXT: addi s7, a1, %lo(__mulsi3)
; RV32I-NEXT: lui a1, 61681
-; RV32I-NEXT: addi s8, a1, -241
-; RV32I-NEXT: and a0, a0, s8
+; RV32I-NEXT: addi s7, a1, -241
+; RV32I-NEXT: and a0, a0, s7
; RV32I-NEXT: mv a1, s4
-; RV32I-NEXT: jalr s7
+; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: addi a0, s2, -1
; RV32I-NEXT: not a1, s2
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: and a0, a0, s8
+; RV32I-NEXT: and a0, a0, s7
; RV32I-NEXT: mv a1, s4
-; RV32I-NEXT: jalr s7
+; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: bnez s3, .LBB11_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: srli a0, s1, 24
; RV32I-NEXT: .LBB11_3:
; RV32I-NEXT: mv a1, zero
-; RV32I-NEXT: lw s8, 12(sp)
-; RV32I-NEXT: lw s7, 16(sp)
-; RV32I-NEXT: lw s6, 20(sp)
-; RV32I-NEXT: lw s5, 24(sp)
-; RV32I-NEXT: lw s4, 28(sp)
-; RV32I-NEXT: lw s3, 32(sp)
-; RV32I-NEXT: lw s2, 36(sp)
-; RV32I-NEXT: lw s1, 40(sp)
-; RV32I-NEXT: lw ra, 44(sp)
-; RV32I-NEXT: addi sp, sp, 48
+; RV32I-NEXT: lw s7, 0(sp)
+; RV32I-NEXT: lw s6, 4(sp)
+; RV32I-NEXT: lw s5, 8(sp)
+; RV32I-NEXT: lw s4, 12(sp)
+; RV32I-NEXT: lw s3, 16(sp)
+; RV32I-NEXT: lw s2, 20(sp)
+; RV32I-NEXT: lw s1, 24(sp)
+; RV32I-NEXT: lw ra, 28(sp)
+; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
%tmp = call i64 @llvm.cttz.i64(i64 %a, i1 true)
ret i64 %tmp
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257
-; RV32I-NEXT: lui a2, %hi(__mulsi3)
-; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
-; RV32I-NEXT: jalr a2
+; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: lui a0, %hi(foo)
; RV32I-NEXT: lw a0, %lo(foo)(a0)
; RV32I-NEXT: sw a0, 12(sp)
-; RV32I-NEXT: lui a0, %hi(callee)
-; RV32I-NEXT: addi a1, a0, %lo(callee)
; RV32I-NEXT: addi a0, sp, 12
-; RV32I-NEXT: jalr a1
+; RV32I-NEXT: call callee
; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a1, %hi(receive_uint8)
-; RV32I-NEXT: addi a1, a1, %lo(receive_uint8)
-; RV32I-NEXT: jalr a1
+; RV32I-NEXT: call receive_uint8
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a0, %hi(return_uint8)
-; RV32I-NEXT: addi a0, a0, %lo(return_uint8)
-; RV32I-NEXT: jalr a0
+; RV32I-NEXT: call return_uint8
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a1, %hi(receive_sint8)
-; RV32I-NEXT: addi a1, a1, %lo(receive_sint8)
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: jalr a1
+; RV32I-NEXT: call receive_sint8
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a0, %hi(return_uint8)
-; RV32I-NEXT: addi a0, a0, %lo(return_uint8)
-; RV32I-NEXT: jalr a0
+; RV32I-NEXT: call return_uint8
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp)
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a1, %hi(receive_anyint32)
-; RV32I-NEXT: addi a1, a1, %lo(receive_anyint32)
-; RV32I-NEXT: jalr a1
+; RV32I-NEXT: call receive_anyint32
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a0, %hi(return_uint8)
-; RV32I-NEXT: addi a0, a0, %lo(return_uint8)
-; RV32I-NEXT: jalr a0
+; RV32I-NEXT: call return_uint8
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: andi a0, a0, 255
-; RV32I-NEXT: lui a1, %hi(receive_uint8)
-; RV32I-NEXT: addi a1, a1, %lo(receive_uint8)
-; RV32I-NEXT: jalr a1
+; RV32I-NEXT: call receive_uint8
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a0, %hi(return_sint8)
-; RV32I-NEXT: addi a0, a0, %lo(return_sint8)
-; RV32I-NEXT: jalr a0
+; RV32I-NEXT: call return_sint8
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a1, %hi(receive_sint8)
-; RV32I-NEXT: addi a1, a1, %lo(receive_sint8)
-; RV32I-NEXT: jalr a1
+; RV32I-NEXT: call receive_sint8
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a0, %hi(return_sint8)
-; RV32I-NEXT: addi a0, a0, %lo(return_sint8)
-; RV32I-NEXT: jalr a0
+; RV32I-NEXT: call return_sint8
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a1, %hi(receive_anyint32)
-; RV32I-NEXT: addi a1, a1, %lo(receive_anyint32)
-; RV32I-NEXT: jalr a1
+; RV32I-NEXT: call receive_anyint32
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a0, %hi(return_sint8)
-; RV32I-NEXT: addi a0, a0, %lo(return_sint8)
-; RV32I-NEXT: jalr a0
+; RV32I-NEXT: call return_sint8
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: andi a0, a0, 255
-; RV32I-NEXT: lui a1, %hi(receive_uint8)
-; RV32I-NEXT: addi a1, a1, %lo(receive_uint8)
-; RV32I-NEXT: jalr a1
+; RV32I-NEXT: call receive_uint8
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a0, %hi(return_anyint32)
-; RV32I-NEXT: addi a0, a0, %lo(return_anyint32)
-; RV32I-NEXT: jalr a0
+; RV32I-NEXT: call return_anyint32
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a1, %hi(receive_sint8)
-; RV32I-NEXT: addi a1, a1, %lo(receive_sint8)
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: jalr a1
+; RV32I-NEXT: call receive_sint8
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a0, %hi(return_anyint32)
-; RV32I-NEXT: addi a0, a0, %lo(return_anyint32)
-; RV32I-NEXT: jalr a0
+; RV32I-NEXT: call return_anyint32
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp)
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a1, %hi(receive_anyint32)
-; RV32I-NEXT: addi a1, a1, %lo(receive_anyint32)
-; RV32I-NEXT: jalr a1
+; RV32I-NEXT: call receive_anyint32
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a0, %hi(return_anyint32)
-; RV32I-NEXT: addi a0, a0, %lo(return_anyint32)
-; RV32I-NEXT: jalr a0
+; RV32I-NEXT: call return_anyint32
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I-FPELIM-NEXT: mv s2, a3
; RV32I-FPELIM-NEXT: mv s3, a1
; RV32I-FPELIM-NEXT: mv s4, a0
-; RV32I-FPELIM-NEXT: lui a0, %hi(__fixdfsi)
-; RV32I-FPELIM-NEXT: addi a2, a0, %lo(__fixdfsi)
; RV32I-FPELIM-NEXT: mv a0, a5
; RV32I-FPELIM-NEXT: mv a1, a6
-; RV32I-FPELIM-NEXT: jalr a2
+; RV32I-FPELIM-NEXT: call __fixdfsi
; RV32I-FPELIM-NEXT: add a1, s4, s3
; RV32I-FPELIM-NEXT: add a1, a1, s2
; RV32I-FPELIM-NEXT: add a1, a1, s1
; RV32I-WITHFP-NEXT: mv s2, a3
; RV32I-WITHFP-NEXT: mv s3, a1
; RV32I-WITHFP-NEXT: mv s4, a0
-; RV32I-WITHFP-NEXT: lui a0, %hi(__fixdfsi)
-; RV32I-WITHFP-NEXT: addi a2, a0, %lo(__fixdfsi)
; RV32I-WITHFP-NEXT: mv a0, a5
; RV32I-WITHFP-NEXT: mv a1, a6
-; RV32I-WITHFP-NEXT: jalr a2
+; RV32I-WITHFP-NEXT: call __fixdfsi
; RV32I-WITHFP-NEXT: add a1, s4, s3
; RV32I-WITHFP-NEXT: add a1, a1, s2
; RV32I-WITHFP-NEXT: add a1, a1, s1
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
-; RV32I-FPELIM-NEXT: lui a0, %hi(callee_scalars)
-; RV32I-FPELIM-NEXT: addi a7, a0, %lo(callee_scalars)
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: addi a3, zero, 3
; RV32I-FPELIM-NEXT: lui a6, 262464
; RV32I-FPELIM-NEXT: mv a2, zero
; RV32I-FPELIM-NEXT: mv a5, zero
-; RV32I-FPELIM-NEXT: jalr a7
+; RV32I-FPELIM-NEXT: call callee_scalars
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
-; RV32I-WITHFP-NEXT: lui a0, %hi(callee_scalars)
-; RV32I-WITHFP-NEXT: addi a7, a0, %lo(callee_scalars)
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: addi a3, zero, 3
; RV32I-WITHFP-NEXT: lui a6, 262464
; RV32I-WITHFP-NEXT: mv a2, zero
; RV32I-WITHFP-NEXT: mv a5, zero
-; RV32I-WITHFP-NEXT: jalr a7
+; RV32I-WITHFP-NEXT: call callee_scalars
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: sw zero, 28(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: sw a0, 24(sp)
-; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_scalars)
-; RV32I-FPELIM-NEXT: addi a2, a0, %lo(callee_large_scalars)
; RV32I-FPELIM-NEXT: addi a0, sp, 24
; RV32I-FPELIM-NEXT: mv a1, sp
-; RV32I-FPELIM-NEXT: jalr a2
+; RV32I-FPELIM-NEXT: call callee_large_scalars
; RV32I-FPELIM-NEXT: lw ra, 44(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 48
; RV32I-FPELIM-NEXT: ret
; RV32I-WITHFP-NEXT: sw zero, -20(s0)
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: sw a0, -24(s0)
-; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_scalars)
-; RV32I-WITHFP-NEXT: addi a2, a0, %lo(callee_large_scalars)
; RV32I-WITHFP-NEXT: addi a0, s0, -24
; RV32I-WITHFP-NEXT: addi a1, s0, -48
-; RV32I-WITHFP-NEXT: jalr a2
+; RV32I-WITHFP-NEXT: call callee_large_scalars
; RV32I-WITHFP-NEXT: lw s0, 40(sp)
; RV32I-WITHFP-NEXT: lw ra, 44(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 48
; RV32I-FPELIM-NEXT: sw zero, 44(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 8
; RV32I-FPELIM-NEXT: sw a0, 40(sp)
-; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_scalars_exhausted_regs)
-; RV32I-FPELIM-NEXT: addi t0, a0, %lo(callee_large_scalars_exhausted_regs)
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: addi a2, zero, 3
; RV32I-FPELIM-NEXT: addi a5, zero, 6
; RV32I-FPELIM-NEXT: addi a6, zero, 7
; RV32I-FPELIM-NEXT: addi a7, sp, 40
-; RV32I-FPELIM-NEXT: jalr t0
+; RV32I-FPELIM-NEXT: call callee_large_scalars_exhausted_regs
; RV32I-FPELIM-NEXT: lw ra, 60(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 64
; RV32I-FPELIM-NEXT: ret
; RV32I-WITHFP-NEXT: sw zero, -20(s0)
; RV32I-WITHFP-NEXT: addi a0, zero, 8
; RV32I-WITHFP-NEXT: sw a0, -24(s0)
-; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_scalars_exhausted_regs)
-; RV32I-WITHFP-NEXT: addi t0, a0, %lo(callee_large_scalars_exhausted_regs)
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: addi a2, zero, 3
; RV32I-WITHFP-NEXT: addi a5, zero, 6
; RV32I-WITHFP-NEXT: addi a6, zero, 7
; RV32I-WITHFP-NEXT: addi a7, s0, -24
-; RV32I-WITHFP-NEXT: jalr t0
+; RV32I-WITHFP-NEXT: call callee_large_scalars_exhausted_regs
; RV32I-WITHFP-NEXT: lw s0, 56(sp)
; RV32I-WITHFP-NEXT: lw ra, 60(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 64
; RV32I-FPELIM-NEXT: sw ra, 28(sp)
; RV32I-FPELIM-NEXT: mv a2, a1
; RV32I-FPELIM-NEXT: mv a1, a0
-; RV32I-FPELIM-NEXT: lui a0, %hi(__floatditf)
-; RV32I-FPELIM-NEXT: addi a3, a0, %lo(__floatditf)
; RV32I-FPELIM-NEXT: addi a0, sp, 8
-; RV32I-FPELIM-NEXT: jalr a3
+; RV32I-FPELIM-NEXT: call __floatditf
; RV32I-FPELIM-NEXT: lw a0, 8(sp)
; RV32I-FPELIM-NEXT: lw ra, 28(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 32
; RV32I-WITHFP-NEXT: addi s0, sp, 32
; RV32I-WITHFP-NEXT: mv a2, a1
; RV32I-WITHFP-NEXT: mv a1, a0
-; RV32I-WITHFP-NEXT: lui a0, %hi(__floatditf)
-; RV32I-WITHFP-NEXT: addi a3, a0, %lo(__floatditf)
; RV32I-WITHFP-NEXT: addi a0, s0, -24
-; RV32I-WITHFP-NEXT: jalr a3
+; RV32I-WITHFP-NEXT: call __floatditf
; RV32I-WITHFP-NEXT: lw a0, -24(s0)
; RV32I-WITHFP-NEXT: lw s0, 24(sp)
; RV32I-WITHFP-NEXT: lw ra, 28(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 8
; RV32I-FPELIM-NEXT: sw a0, 4(sp)
; RV32I-FPELIM-NEXT: sw zero, 0(sp)
-; RV32I-FPELIM-NEXT: lui a0, %hi(callee_many_scalars)
-; RV32I-FPELIM-NEXT: addi t0, a0, %lo(callee_many_scalars)
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: addi a2, zero, 3
; RV32I-FPELIM-NEXT: addi a6, zero, 6
; RV32I-FPELIM-NEXT: addi a7, zero, 7
; RV32I-FPELIM-NEXT: mv a4, zero
-; RV32I-FPELIM-NEXT: jalr t0
+; RV32I-FPELIM-NEXT: call callee_many_scalars
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
; RV32I-WITHFP-NEXT: addi a0, zero, 8
; RV32I-WITHFP-NEXT: sw a0, 4(sp)
; RV32I-WITHFP-NEXT: sw zero, 0(sp)
-; RV32I-WITHFP-NEXT: lui a0, %hi(callee_many_scalars)
-; RV32I-WITHFP-NEXT: addi t0, a0, %lo(callee_many_scalars)
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: addi a2, zero, 3
; RV32I-WITHFP-NEXT: addi a6, zero, 6
; RV32I-WITHFP-NEXT: addi a7, zero, 7
; RV32I-WITHFP-NEXT: mv a4, zero
-; RV32I-WITHFP-NEXT: jalr t0
+; RV32I-WITHFP-NEXT: call callee_many_scalars
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
-; RV32I-FPELIM-NEXT: lui a0, %hi(callee_small_coerced_struct)
-; RV32I-FPELIM-NEXT: addi a2, a0, %lo(callee_small_coerced_struct)
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2
-; RV32I-FPELIM-NEXT: jalr a2
+; RV32I-FPELIM-NEXT: call callee_small_coerced_struct
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
-; RV32I-WITHFP-NEXT: lui a0, %hi(callee_small_coerced_struct)
-; RV32I-WITHFP-NEXT: addi a2, a0, %lo(callee_small_coerced_struct)
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2
-; RV32I-WITHFP-NEXT: jalr a2
+; RV32I-WITHFP-NEXT: call callee_small_coerced_struct
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: addi a0, zero, 4
; RV32I-FPELIM-NEXT: sw a0, 36(sp)
; RV32I-FPELIM-NEXT: sw a0, 20(sp)
-; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_struct)
-; RV32I-FPELIM-NEXT: addi a1, a0, %lo(callee_large_struct)
; RV32I-FPELIM-NEXT: addi a0, sp, 8
-; RV32I-FPELIM-NEXT: jalr a1
+; RV32I-FPELIM-NEXT: call callee_large_struct
; RV32I-FPELIM-NEXT: lw ra, 44(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 48
; RV32I-FPELIM-NEXT: ret
; RV32I-WITHFP-NEXT: addi a0, zero, 4
; RV32I-WITHFP-NEXT: sw a0, -12(s0)
; RV32I-WITHFP-NEXT: sw a0, -28(s0)
-; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_struct)
-; RV32I-WITHFP-NEXT: addi a1, a0, %lo(callee_large_struct)
; RV32I-WITHFP-NEXT: addi a0, s0, -40
-; RV32I-WITHFP-NEXT: jalr a1
+; RV32I-WITHFP-NEXT: call callee_large_struct
; RV32I-WITHFP-NEXT: lw s0, 40(sp)
; RV32I-WITHFP-NEXT: lw ra, 44(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 48
; RV32I-FPELIM-NEXT: sw a0, 32(sp)
; RV32I-FPELIM-NEXT: lui a0, 688509
; RV32I-FPELIM-NEXT: addi a5, a0, -2048
-; RV32I-FPELIM-NEXT: lui a0, %hi(callee_aligned_stack)
-; RV32I-FPELIM-NEXT: addi t0, a0, %lo(callee_aligned_stack)
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 11
; RV32I-FPELIM-NEXT: addi a2, sp, 32
; RV32I-FPELIM-NEXT: addi a4, zero, 13
; RV32I-FPELIM-NEXT: addi a6, zero, 4
; RV32I-FPELIM-NEXT: addi a7, zero, 14
-; RV32I-FPELIM-NEXT: jalr t0
+; RV32I-FPELIM-NEXT: call callee_aligned_stack
; RV32I-FPELIM-NEXT: lw ra, 60(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 64
; RV32I-FPELIM-NEXT: ret
; RV32I-WITHFP-NEXT: sw a0, -32(s0)
; RV32I-WITHFP-NEXT: lui a0, 688509
; RV32I-WITHFP-NEXT: addi a5, a0, -2048
-; RV32I-WITHFP-NEXT: lui a0, %hi(callee_aligned_stack)
-; RV32I-WITHFP-NEXT: addi t0, a0, %lo(callee_aligned_stack)
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 11
; RV32I-WITHFP-NEXT: addi a2, s0, -32
; RV32I-WITHFP-NEXT: addi a4, zero, 13
; RV32I-WITHFP-NEXT: addi a6, zero, 4
; RV32I-WITHFP-NEXT: addi a7, zero, 14
-; RV32I-WITHFP-NEXT: jalr t0
+; RV32I-WITHFP-NEXT: call callee_aligned_stack
; RV32I-WITHFP-NEXT: lw s0, 56(sp)
; RV32I-WITHFP-NEXT: lw ra, 60(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 64
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
-; RV32I-FPELIM-NEXT: lui a0, %hi(callee_small_scalar_ret)
-; RV32I-FPELIM-NEXT: addi a0, a0, %lo(callee_small_scalar_ret)
-; RV32I-FPELIM-NEXT: jalr a0
-; RV32I-FPELIM-NEXT: lui a2, 56
-; RV32I-FPELIM-NEXT: addi a2, a2, 580
-; RV32I-FPELIM-NEXT: xor a1, a1, a2
+; RV32I-FPELIM-NEXT: sw s1, 8(sp)
+; RV32I-FPELIM-NEXT: lui a0, 56
+; RV32I-FPELIM-NEXT: addi s1, a0, 580
+; RV32I-FPELIM-NEXT: call callee_small_scalar_ret
+; RV32I-FPELIM-NEXT: xor a1, a1, s1
; RV32I-FPELIM-NEXT: lui a2, 200614
; RV32I-FPELIM-NEXT: addi a2, a2, 647
; RV32I-FPELIM-NEXT: xor a0, a0, a2
; RV32I-FPELIM-NEXT: or a0, a0, a1
; RV32I-FPELIM-NEXT: xor a0, a0, zero
; RV32I-FPELIM-NEXT: seqz a0, a0
+; RV32I-FPELIM-NEXT: lw s1, 8(sp)
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
+; RV32I-WITHFP-NEXT: sw s1, 4(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
-; RV32I-WITHFP-NEXT: lui a0, %hi(callee_small_scalar_ret)
-; RV32I-WITHFP-NEXT: addi a0, a0, %lo(callee_small_scalar_ret)
-; RV32I-WITHFP-NEXT: jalr a0
-; RV32I-WITHFP-NEXT: lui a2, 56
-; RV32I-WITHFP-NEXT: addi a2, a2, 580
-; RV32I-WITHFP-NEXT: xor a1, a1, a2
+; RV32I-WITHFP-NEXT: lui a0, 56
+; RV32I-WITHFP-NEXT: addi s1, a0, 580
+; RV32I-WITHFP-NEXT: call callee_small_scalar_ret
+; RV32I-WITHFP-NEXT: xor a1, a1, s1
; RV32I-WITHFP-NEXT: lui a2, 200614
; RV32I-WITHFP-NEXT: addi a2, a2, 647
; RV32I-WITHFP-NEXT: xor a0, a0, a2
; RV32I-WITHFP-NEXT: or a0, a0, a1
; RV32I-WITHFP-NEXT: xor a0, a0, zero
; RV32I-WITHFP-NEXT: seqz a0, a0
+; RV32I-WITHFP-NEXT: lw s1, 4(sp)
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
-; RV32I-FPELIM-NEXT: lui a0, %hi(callee_small_struct_ret)
-; RV32I-FPELIM-NEXT: addi a0, a0, %lo(callee_small_struct_ret)
-; RV32I-FPELIM-NEXT: jalr a0
+; RV32I-FPELIM-NEXT: call callee_small_struct_ret
; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
-; RV32I-WITHFP-NEXT: lui a0, %hi(callee_small_struct_ret)
-; RV32I-WITHFP-NEXT: addi a0, a0, %lo(callee_small_struct_ret)
-; RV32I-WITHFP-NEXT: jalr a0
+; RV32I-WITHFP-NEXT: call callee_small_struct_ret
; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -32
; RV32I-FPELIM-NEXT: sw ra, 28(sp)
-; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_scalar_ret)
-; RV32I-FPELIM-NEXT: addi a1, a0, %lo(callee_large_scalar_ret)
; RV32I-FPELIM-NEXT: mv a0, sp
-; RV32I-FPELIM-NEXT: jalr a1
+; RV32I-FPELIM-NEXT: call callee_large_scalar_ret
; RV32I-FPELIM-NEXT: lw ra, 28(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 32
; RV32I-FPELIM-NEXT: ret
; RV32I-WITHFP-NEXT: sw ra, 28(sp)
; RV32I-WITHFP-NEXT: sw s0, 24(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 32
-; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_scalar_ret)
-; RV32I-WITHFP-NEXT: addi a1, a0, %lo(callee_large_scalar_ret)
; RV32I-WITHFP-NEXT: addi a0, s0, -32
-; RV32I-WITHFP-NEXT: jalr a1
+; RV32I-WITHFP-NEXT: call callee_large_scalar_ret
; RV32I-WITHFP-NEXT: lw s0, 24(sp)
; RV32I-WITHFP-NEXT: lw ra, 28(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 32
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -32
; RV32I-FPELIM-NEXT: sw ra, 28(sp)
-; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_struct_ret)
-; RV32I-FPELIM-NEXT: addi a1, a0, %lo(callee_large_struct_ret)
; RV32I-FPELIM-NEXT: addi a0, sp, 8
-; RV32I-FPELIM-NEXT: jalr a1
+; RV32I-FPELIM-NEXT: call callee_large_struct_ret
; RV32I-FPELIM-NEXT: lw a0, 20(sp)
; RV32I-FPELIM-NEXT: lw a1, 8(sp)
; RV32I-FPELIM-NEXT: add a0, a1, a0
; RV32I-WITHFP-NEXT: sw ra, 28(sp)
; RV32I-WITHFP-NEXT: sw s0, 24(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 32
-; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_struct_ret)
-; RV32I-WITHFP-NEXT: addi a1, a0, %lo(callee_large_struct_ret)
; RV32I-WITHFP-NEXT: addi a0, s0, -24
-; RV32I-WITHFP-NEXT: jalr a1
+; RV32I-WITHFP-NEXT: call callee_large_struct_ret
; RV32I-WITHFP-NEXT: lw a0, -12(s0)
; RV32I-WITHFP-NEXT: lw a1, -24(s0)
; RV32I-WITHFP-NEXT: add a0, a1, a0
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a1, %hi(external_function)
-; RV32I-NEXT: addi a1, a1, %lo(external_function)
-; RV32I-NEXT: jalr a1
+; RV32I-NEXT: call external_function
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a1, %hi(defined_function)
-; RV32I-NEXT: addi a1, a1, %lo(defined_function)
-; RV32I-NEXT: jalr a1
+; RV32I-NEXT: call defined_function
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s1, 8(sp)
; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lui a0, %hi(fastcc_function)
-; RV32I-NEXT: addi a2, a0, %lo(fastcc_function)
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: jalr a2
+; RV32I-NEXT: call fastcc_function
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: lw s1, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: sw a0, 4(sp)
; RV32I-NEXT: sw a0, 0(sp)
-; RV32I-NEXT: lui a0, %hi(external_many_args)
-; RV32I-NEXT: addi t0, a0, %lo(external_many_args)
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s1
-; RV32I-NEXT: mv a2, s1
-; RV32I-NEXT: mv a3, s1
-; RV32I-NEXT: mv a4, s1
-; RV32I-NEXT: mv a5, s1
-; RV32I-NEXT: mv a6, s1
-; RV32I-NEXT: mv a7, s1
-; RV32I-NEXT: jalr t0
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: mv a3, a0
+; RV32I-NEXT: mv a4, a0
+; RV32I-NEXT: mv a5, a0
+; RV32I-NEXT: mv a6, a0
+; RV32I-NEXT: mv a7, a0
+; RV32I-NEXT: call external_many_args
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: lw s1, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw a0, 4(sp)
; RV32I-NEXT: sw a0, 0(sp)
-; RV32I-NEXT: lui a1, %hi(defined_many_args)
-; RV32I-NEXT: addi t0, a1, %lo(defined_many_args)
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a3, a0
; RV32I-NEXT: mv a5, a0
; RV32I-NEXT: mv a6, a0
; RV32I-NEXT: mv a7, a0
-; RV32I-NEXT: jalr t0
+; RV32I-NEXT: call defined_many_args
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a2, %hi(__udivsi3)
-; RV32I-NEXT: addi a2, a2, %lo(__udivsi3)
-; RV32I-NEXT: jalr a2
+; RV32I-NEXT: call __udivsi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a1, %hi(__udivsi3)
-; RV32I-NEXT: addi a2, a1, %lo(__udivsi3)
; RV32I-NEXT: addi a1, zero, 5
-; RV32I-NEXT: jalr a2
+; RV32I-NEXT: call __udivsi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a4, %hi(__udivdi3)
-; RV32I-NEXT: addi a4, a4, %lo(__udivdi3)
-; RV32I-NEXT: jalr a4
+; RV32I-NEXT: call __udivdi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -16
; RV32IM-NEXT: sw ra, 12(sp)
-; RV32IM-NEXT: lui a4, %hi(__udivdi3)
-; RV32IM-NEXT: addi a4, a4, %lo(__udivdi3)
-; RV32IM-NEXT: jalr a4
+; RV32IM-NEXT: call __udivdi3
; RV32IM-NEXT: lw ra, 12(sp)
; RV32IM-NEXT: addi sp, sp, 16
; RV32IM-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a2, %hi(__udivdi3)
-; RV32I-NEXT: addi a4, a2, %lo(__udivdi3)
; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: mv a3, zero
-; RV32I-NEXT: jalr a4
+; RV32I-NEXT: call __udivdi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -16
; RV32IM-NEXT: sw ra, 12(sp)
-; RV32IM-NEXT: lui a2, %hi(__udivdi3)
-; RV32IM-NEXT: addi a4, a2, %lo(__udivdi3)
; RV32IM-NEXT: addi a2, zero, 5
; RV32IM-NEXT: mv a3, zero
-; RV32IM-NEXT: jalr a4
+; RV32IM-NEXT: call __udivdi3
; RV32IM-NEXT: lw ra, 12(sp)
; RV32IM-NEXT: addi sp, sp, 16
; RV32IM-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a2, %hi(__divsi3)
-; RV32I-NEXT: addi a2, a2, %lo(__divsi3)
-; RV32I-NEXT: jalr a2
+; RV32I-NEXT: call __divsi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a1, %hi(__divsi3)
-; RV32I-NEXT: addi a2, a1, %lo(__divsi3)
; RV32I-NEXT: addi a1, zero, 5
-; RV32I-NEXT: jalr a2
+; RV32I-NEXT: call __divsi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a4, %hi(__divdi3)
-; RV32I-NEXT: addi a4, a4, %lo(__divdi3)
-; RV32I-NEXT: jalr a4
+; RV32I-NEXT: call __divdi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -16
; RV32IM-NEXT: sw ra, 12(sp)
-; RV32IM-NEXT: lui a4, %hi(__divdi3)
-; RV32IM-NEXT: addi a4, a4, %lo(__divdi3)
-; RV32IM-NEXT: jalr a4
+; RV32IM-NEXT: call __divdi3
; RV32IM-NEXT: lw ra, 12(sp)
; RV32IM-NEXT: addi sp, sp, 16
; RV32IM-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a2, %hi(__divdi3)
-; RV32I-NEXT: addi a4, a2, %lo(__divdi3)
; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: mv a3, zero
-; RV32I-NEXT: jalr a4
+; RV32I-NEXT: call __divdi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -16
; RV32IM-NEXT: sw ra, 12(sp)
-; RV32IM-NEXT: lui a2, %hi(__divdi3)
-; RV32IM-NEXT: addi a4, a2, %lo(__divdi3)
; RV32IM-NEXT: addi a2, zero, 5
; RV32IM-NEXT: mv a3, zero
-; RV32IM-NEXT: jalr a4
+; RV32IM-NEXT: call __divdi3
; RV32IM-NEXT: lw ra, 12(sp)
; RV32IM-NEXT: addi sp, sp, 16
; RV32IM-NEXT: ret
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB0_2: # %if.else
-; RV32IFD-NEXT: lui a0, %hi(abort)
-; RV32IFD-NEXT: addi a0, a0, %lo(abort)
-; RV32IFD-NEXT: jalr a0
+; RV32IFD-NEXT: call abort
%1 = fcmp false double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB1_2: # %if.then
-; RV32IFD-NEXT: lui a0, %hi(abort)
-; RV32IFD-NEXT: addi a0, a0, %lo(abort)
-; RV32IFD-NEXT: jalr a0
+; RV32IFD-NEXT: call abort
%1 = fcmp oeq double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB2_2: # %if.then
-; RV32IFD-NEXT: lui a0, %hi(abort)
-; RV32IFD-NEXT: addi a0, a0, %lo(abort)
-; RV32IFD-NEXT: jalr a0
+; RV32IFD-NEXT: call abort
%1 = fcmp oeq double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB3_2: # %if.then
-; RV32IFD-NEXT: lui a0, %hi(abort)
-; RV32IFD-NEXT: addi a0, a0, %lo(abort)
-; RV32IFD-NEXT: jalr a0
+; RV32IFD-NEXT: call abort
%1 = fcmp ogt double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB4_2: # %if.then
-; RV32IFD-NEXT: lui a0, %hi(abort)
-; RV32IFD-NEXT: addi a0, a0, %lo(abort)
-; RV32IFD-NEXT: jalr a0
+; RV32IFD-NEXT: call abort
%1 = fcmp oge double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB5_2: # %if.then
-; RV32IFD-NEXT: lui a0, %hi(abort)
-; RV32IFD-NEXT: addi a0, a0, %lo(abort)
-; RV32IFD-NEXT: jalr a0
+; RV32IFD-NEXT: call abort
%1 = fcmp olt double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB6_2: # %if.then
-; RV32IFD-NEXT: lui a0, %hi(abort)
-; RV32IFD-NEXT: addi a0, a0, %lo(abort)
-; RV32IFD-NEXT: jalr a0
+; RV32IFD-NEXT: call abort
%1 = fcmp ole double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB7_2: # %if.then
-; RV32IFD-NEXT: lui a0, %hi(abort)
-; RV32IFD-NEXT: addi a0, a0, %lo(abort)
-; RV32IFD-NEXT: jalr a0
+; RV32IFD-NEXT: call abort
%1 = fcmp one double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB8_2: # %if.then
-; RV32IFD-NEXT: lui a0, %hi(abort)
-; RV32IFD-NEXT: addi a0, a0, %lo(abort)
-; RV32IFD-NEXT: jalr a0
+; RV32IFD-NEXT: call abort
%1 = fcmp ord double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB9_2: # %if.then
-; RV32IFD-NEXT: lui a0, %hi(abort)
-; RV32IFD-NEXT: addi a0, a0, %lo(abort)
-; RV32IFD-NEXT: jalr a0
+; RV32IFD-NEXT: call abort
%1 = fcmp ueq double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB10_2: # %if.then
-; RV32IFD-NEXT: lui a0, %hi(abort)
-; RV32IFD-NEXT: addi a0, a0, %lo(abort)
-; RV32IFD-NEXT: jalr a0
+; RV32IFD-NEXT: call abort
%1 = fcmp ugt double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB11_2: # %if.then
-; RV32IFD-NEXT: lui a0, %hi(abort)
-; RV32IFD-NEXT: addi a0, a0, %lo(abort)
-; RV32IFD-NEXT: jalr a0
+; RV32IFD-NEXT: call abort
%1 = fcmp uge double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB12_2: # %if.then
-; RV32IFD-NEXT: lui a0, %hi(abort)
-; RV32IFD-NEXT: addi a0, a0, %lo(abort)
-; RV32IFD-NEXT: jalr a0
+; RV32IFD-NEXT: call abort
%1 = fcmp ult double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB13_2: # %if.then
-; RV32IFD-NEXT: lui a0, %hi(abort)
-; RV32IFD-NEXT: addi a0, a0, %lo(abort)
-; RV32IFD-NEXT: jalr a0
+; RV32IFD-NEXT: call abort
%1 = fcmp ule double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB14_2: # %if.then
-; RV32IFD-NEXT: lui a0, %hi(abort)
-; RV32IFD-NEXT: addi a0, a0, %lo(abort)
-; RV32IFD-NEXT: jalr a0
+; RV32IFD-NEXT: call abort
%1 = fcmp une double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB15_2: # %if.then
-; RV32IFD-NEXT: lui a0, %hi(abort)
-; RV32IFD-NEXT: addi a0, a0, %lo(abort)
-; RV32IFD-NEXT: jalr a0
+; RV32IFD-NEXT: call abort
%1 = fcmp uno double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB16_2: # %if.then
-; RV32IFD-NEXT: lui a0, %hi(abort)
-; RV32IFD-NEXT: addi a0, a0, %lo(abort)
-; RV32IFD-NEXT: jalr a0
+; RV32IFD-NEXT: call abort
%1 = fcmp true double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp)
-; RV32IFD-NEXT: lui a0, %hi(callee_double_inreg)
-; RV32IFD-NEXT: addi a4, a0, %lo(callee_double_inreg)
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_0)
; RV32IFD-NEXT: fld ft0, 0(a0)
; RV32IFD-NEXT: fsd ft0, 0(sp)
; RV32IFD-NEXT: lw a2, 0(sp)
; RV32IFD-NEXT: lw a3, 4(sp)
-; RV32IFD-NEXT: jalr a4
+; RV32IFD-NEXT: call callee_double_inreg
; RV32IFD-NEXT: lw ra, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: lw a7, 16(sp)
; RV32IFD-NEXT: lw a0, 20(sp)
; RV32IFD-NEXT: sw a0, 0(sp)
-; RV32IFD-NEXT: lui a0, %hi(callee_double_split_reg_stack)
-; RV32IFD-NEXT: addi t0, a0, %lo(callee_double_split_reg_stack)
; RV32IFD-NEXT: lui a0, %hi(.LCPI3_1)
; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI3_1)
; RV32IFD-NEXT: fld ft0, 0(a0)
; RV32IFD-NEXT: addi a3, zero, 3
; RV32IFD-NEXT: mv a2, zero
; RV32IFD-NEXT: mv a4, zero
-; RV32IFD-NEXT: jalr t0
+; RV32IFD-NEXT: call callee_double_split_reg_stack
; RV32IFD-NEXT: lw ra, 28(sp)
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: addi a0, a0, -1311
; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
-; RV32IFD-NEXT: lui a0, %hi(callee_double_stack)
-; RV32IFD-NEXT: addi t0, a0, %lo(callee_double_stack)
; RV32IFD-NEXT: addi a0, zero, 1
; RV32IFD-NEXT: addi a2, zero, 2
; RV32IFD-NEXT: addi a4, zero, 3
; RV32IFD-NEXT: mv a3, zero
; RV32IFD-NEXT: mv a5, zero
; RV32IFD-NEXT: mv a7, zero
-; RV32IFD-NEXT: jalr t0
+; RV32IFD-NEXT: call callee_double_stack
; RV32IFD-NEXT: lw ra, 28(sp)
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp)
-; RV32IFD-NEXT: lui a2, %hi(floor)
-; RV32IFD-NEXT: addi a2, a2, %lo(floor)
-; RV32IFD-NEXT: jalr a2
+; RV32IFD-NEXT: call floor
; RV32IFD-NEXT: lw ra, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: sw s2, 20(sp)
; RV32IFD-NEXT: mv s1, a1
; RV32IFD-NEXT: mv s2, a0
-; RV32IFD-NEXT: lui a0, %hi(notdead)
-; RV32IFD-NEXT: addi a1, a0, %lo(notdead)
; RV32IFD-NEXT: addi a0, sp, 8
-; RV32IFD-NEXT: jalr a1
+; RV32IFD-NEXT: call notdead
; RV32IFD-NEXT: sw s2, 0(sp)
; RV32IFD-NEXT: sw s1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; RV32IFD-NEXT: fsd ft0, 16(sp)
-; RV32IFD-NEXT: lui a0, %hi(notdead)
-; RV32IFD-NEXT: addi a1, a0, %lo(notdead)
; RV32IFD-NEXT: addi a0, sp, 16
-; RV32IFD-NEXT: jalr a1
+; RV32IFD-NEXT: call notdead
; RV32IFD-NEXT: lw ra, 28(sp)
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
; RV32IFD: # %bb.0: # %entry
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp)
-; RV32IFD-NEXT: lui a0, %hi(test)
-; RV32IFD-NEXT: addi a2, a0, %lo(test)
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_0)
; RV32IFD-NEXT: fld ft0, 0(a0)
; RV32IFD-NEXT: fsd ft0, 0(sp)
; RV32IFD-NEXT: lw a0, 0(sp)
; RV32IFD-NEXT: lw a1, 4(sp)
-; RV32IFD-NEXT: jalr a2
+; RV32IFD-NEXT: call test
+; RV32IFD-NEXT: lui a2, %hi(.LCPI1_1)
+; RV32IFD-NEXT: addi a2, a2, %lo(.LCPI1_1)
+; RV32IFD-NEXT: fld ft1, 0(a2)
; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp)
-; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
-; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_1)
-; RV32IFD-NEXT: fld ft1, 0(a0)
; RV32IFD-NEXT: flt.d a0, ft0, ft1
; RV32IFD-NEXT: bnez a0, .LBB1_3
; RV32IFD-NEXT: # %bb.1: # %entry
; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: beqz a0, .LBB1_3
; RV32IFD-NEXT: # %bb.2: # %if.end
-; RV32IFD-NEXT: lui a0, %hi(exit)
-; RV32IFD-NEXT: addi a1, a0, %lo(exit)
; RV32IFD-NEXT: mv a0, zero
-; RV32IFD-NEXT: jalr a1
+; RV32IFD-NEXT: call exit
; RV32IFD-NEXT: .LBB1_3: # %if.then
-; RV32IFD-NEXT: lui a0, %hi(abort)
-; RV32IFD-NEXT: addi a0, a0, %lo(abort)
-; RV32IFD-NEXT: jalr a0
+; RV32IFD-NEXT: call abort
entry:
%call = call double @test(double 2.000000e+00)
%cmp = fcmp olt double %call, 2.400000e-01
; RV32IFD-NEXT: beqz a2, .LBB0_2
; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: addi a2, a2, -1
-; RV32IFD-NEXT: lui a0, %hi(func)
-; RV32IFD-NEXT: addi a3, a0, %lo(func)
; RV32IFD-NEXT: fsd ft0, 16(sp)
; RV32IFD-NEXT: lw a0, 16(sp)
; RV32IFD-NEXT: lw a1, 20(sp)
; RV32IFD-NEXT: fsd ft0, 8(sp)
-; RV32IFD-NEXT: jalr a3
+; RV32IFD-NEXT: call func
; RV32IFD-NEXT: sw a0, 16(sp)
; RV32IFD-NEXT: sw a1, 20(sp)
; RV32IFD-NEXT: fld ft0, 16(sp)
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB0_2: # %if.else
-; RV32IF-NEXT: lui a0, %hi(abort)
-; RV32IF-NEXT: addi a0, a0, %lo(abort)
-; RV32IF-NEXT: jalr a0
+; RV32IF-NEXT: call abort
%1 = fcmp false float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB1_2: # %if.then
-; RV32IF-NEXT: lui a0, %hi(abort)
-; RV32IF-NEXT: addi a0, a0, %lo(abort)
-; RV32IF-NEXT: jalr a0
+; RV32IF-NEXT: call abort
%1 = fcmp oeq float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB2_2: # %if.then
-; RV32IF-NEXT: lui a0, %hi(abort)
-; RV32IF-NEXT: addi a0, a0, %lo(abort)
-; RV32IF-NEXT: jalr a0
+; RV32IF-NEXT: call abort
%1 = fcmp oeq float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB3_2: # %if.then
-; RV32IF-NEXT: lui a0, %hi(abort)
-; RV32IF-NEXT: addi a0, a0, %lo(abort)
-; RV32IF-NEXT: jalr a0
+; RV32IF-NEXT: call abort
%1 = fcmp ogt float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB4_2: # %if.then
-; RV32IF-NEXT: lui a0, %hi(abort)
-; RV32IF-NEXT: addi a0, a0, %lo(abort)
-; RV32IF-NEXT: jalr a0
+; RV32IF-NEXT: call abort
%1 = fcmp oge float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB5_2: # %if.then
-; RV32IF-NEXT: lui a0, %hi(abort)
-; RV32IF-NEXT: addi a0, a0, %lo(abort)
-; RV32IF-NEXT: jalr a0
+; RV32IF-NEXT: call abort
%1 = fcmp olt float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB6_2: # %if.then
-; RV32IF-NEXT: lui a0, %hi(abort)
-; RV32IF-NEXT: addi a0, a0, %lo(abort)
-; RV32IF-NEXT: jalr a0
+; RV32IF-NEXT: call abort
%1 = fcmp ole float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB7_2: # %if.then
-; RV32IF-NEXT: lui a0, %hi(abort)
-; RV32IF-NEXT: addi a0, a0, %lo(abort)
-; RV32IF-NEXT: jalr a0
+; RV32IF-NEXT: call abort
%1 = fcmp one float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB8_2: # %if.then
-; RV32IF-NEXT: lui a0, %hi(abort)
-; RV32IF-NEXT: addi a0, a0, %lo(abort)
-; RV32IF-NEXT: jalr a0
+; RV32IF-NEXT: call abort
%1 = fcmp ord float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB9_2: # %if.then
-; RV32IF-NEXT: lui a0, %hi(abort)
-; RV32IF-NEXT: addi a0, a0, %lo(abort)
-; RV32IF-NEXT: jalr a0
+; RV32IF-NEXT: call abort
%1 = fcmp ueq float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB10_2: # %if.then
-; RV32IF-NEXT: lui a0, %hi(abort)
-; RV32IF-NEXT: addi a0, a0, %lo(abort)
-; RV32IF-NEXT: jalr a0
+; RV32IF-NEXT: call abort
%1 = fcmp ugt float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB11_2: # %if.then
-; RV32IF-NEXT: lui a0, %hi(abort)
-; RV32IF-NEXT: addi a0, a0, %lo(abort)
-; RV32IF-NEXT: jalr a0
+; RV32IF-NEXT: call abort
%1 = fcmp uge float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB12_2: # %if.then
-; RV32IF-NEXT: lui a0, %hi(abort)
-; RV32IF-NEXT: addi a0, a0, %lo(abort)
-; RV32IF-NEXT: jalr a0
+; RV32IF-NEXT: call abort
%1 = fcmp ult float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB13_2: # %if.then
-; RV32IF-NEXT: lui a0, %hi(abort)
-; RV32IF-NEXT: addi a0, a0, %lo(abort)
-; RV32IF-NEXT: jalr a0
+; RV32IF-NEXT: call abort
%1 = fcmp ule float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB14_2: # %if.then
-; RV32IF-NEXT: lui a0, %hi(abort)
-; RV32IF-NEXT: addi a0, a0, %lo(abort)
-; RV32IF-NEXT: jalr a0
+; RV32IF-NEXT: call abort
%1 = fcmp une float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB15_2: # %if.then
-; RV32IF-NEXT: lui a0, %hi(abort)
-; RV32IF-NEXT: addi a0, a0, %lo(abort)
-; RV32IF-NEXT: jalr a0
+; RV32IF-NEXT: call abort
%1 = fcmp uno float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB16_2: # %if.then
-; RV32IF-NEXT: lui a0, %hi(abort)
-; RV32IF-NEXT: addi a0, a0, %lo(abort)
-; RV32IF-NEXT: jalr a0
+; RV32IF-NEXT: call abort
%1 = fcmp true float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
; RV32IF: # %bb.0: # %entry
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
-; RV32IF-NEXT: sw s1, 8(sp)
-; RV32IF-NEXT: lui a0, %hi(dummy)
-; RV32IF-NEXT: addi s1, a0, %lo(dummy)
; RV32IF-NEXT: mv a0, zero
-; RV32IF-NEXT: jalr s1
+; RV32IF-NEXT: call dummy
+; RV32IF-NEXT: lui a1, %hi(.LCPI17_0)
+; RV32IF-NEXT: addi a1, a1, %lo(.LCPI17_0)
+; RV32IF-NEXT: flw ft1, 0(a1)
; RV32IF-NEXT: fmv.w.x ft0, a0
-; RV32IF-NEXT: lui a0, %hi(.LCPI17_0)
-; RV32IF-NEXT: addi a0, a0, %lo(.LCPI17_0)
-; RV32IF-NEXT: flw ft1, 0(a0)
-; RV32IF-NEXT: fsw ft1, 4(sp)
+; RV32IF-NEXT: fsw ft1, 8(sp)
; RV32IF-NEXT: feq.s a0, ft0, ft1
; RV32IF-NEXT: beqz a0, .LBB17_3
; RV32IF-NEXT: # %bb.1: # %if.end
; RV32IF-NEXT: mv a0, zero
-; RV32IF-NEXT: jalr s1
+; RV32IF-NEXT: call dummy
; RV32IF-NEXT: fmv.w.x ft0, a0
-; RV32IF-NEXT: flw ft1, 4(sp)
+; RV32IF-NEXT: flw ft1, 8(sp)
; RV32IF-NEXT: feq.s a0, ft0, ft1
; RV32IF-NEXT: beqz a0, .LBB17_3
; RV32IF-NEXT: # %bb.2: # %if.end4
; RV32IF-NEXT: mv a0, zero
-; RV32IF-NEXT: lw s1, 8(sp)
; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB17_3: # %if.then
-; RV32IF-NEXT: lui a0, %hi(abort)
-; RV32IF-NEXT: addi a0, a0, %lo(abort)
-; RV32IF-NEXT: jalr a0
+; RV32IF-NEXT: call abort
entry:
%call = call float @dummy(float 0.000000e+00)
%cmp = fcmp une float %call, 0.000000e+00
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: sw s1, 8(sp)
; RV32IF-NEXT: mv s1, a0
-; RV32IF-NEXT: lui a0, %hi(notdead)
-; RV32IF-NEXT: addi a1, a0, %lo(notdead)
; RV32IF-NEXT: addi a0, sp, 4
-; RV32IF-NEXT: jalr a1
+; RV32IF-NEXT: call notdead
; RV32IF-NEXT: fmv.w.x ft0, s1
; RV32IF-NEXT: flw ft1, 4(sp)
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fsw ft0, 8(sp)
-; RV32IF-NEXT: lui a0, %hi(notdead)
-; RV32IF-NEXT: addi a1, a0, %lo(notdead)
; RV32IF-NEXT: addi a0, sp, 8
-; RV32IF-NEXT: jalr a1
+; RV32IF-NEXT: call notdead
; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32I-NEXT: lui a0, %hi(x)
; RV32I-NEXT: lw a0, %lo(x)(a0)
; RV32I-NEXT: sw a0, 24(sp)
-; RV32I-NEXT: lui a0, %hi(__netf2)
-; RV32I-NEXT: addi a2, a0, %lo(__netf2)
; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8
-; RV32I-NEXT: jalr a2
+; RV32I-NEXT: call __netf2
; RV32I-NEXT: xor a0, a0, zero
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: lui a0, %hi(x)
; RV32I-NEXT: lw a0, %lo(x)(a0)
; RV32I-NEXT: sw a0, 40(sp)
-; RV32I-NEXT: lui a0, %hi(__addtf3)
-; RV32I-NEXT: addi a3, a0, %lo(__addtf3)
; RV32I-NEXT: addi a0, sp, 56
; RV32I-NEXT: addi a1, sp, 40
; RV32I-NEXT: addi a2, sp, 24
-; RV32I-NEXT: jalr a3
+; RV32I-NEXT: call __addtf3
; RV32I-NEXT: lw a0, 68(sp)
; RV32I-NEXT: sw a0, 20(sp)
; RV32I-NEXT: lw a0, 64(sp)
; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: lw a0, 56(sp)
; RV32I-NEXT: sw a0, 8(sp)
-; RV32I-NEXT: lui a0, %hi(__fixtfsi)
-; RV32I-NEXT: addi a1, a0, %lo(__fixtfsi)
; RV32I-NEXT: addi a0, sp, 8
-; RV32I-NEXT: jalr a1
+; RV32I-NEXT: call __fixtfsi
; RV32I-NEXT: lw ra, 76(sp)
; RV32I-NEXT: addi sp, sp, 80
; RV32I-NEXT: ret
; RV32I-FPELIM-NEXT: sw zero, 16(sp)
; RV32I-FPELIM-NEXT: sw zero, 12(sp)
; RV32I-FPELIM-NEXT: sw zero, 8(sp)
-; RV32I-FPELIM-NEXT: lui a0, %hi(test1)
-; RV32I-FPELIM-NEXT: addi a1, a0, %lo(test1)
; RV32I-FPELIM-NEXT: addi a0, sp, 12
-; RV32I-FPELIM-NEXT: jalr a1
+; RV32I-FPELIM-NEXT: call test1
; RV32I-FPELIM-NEXT: mv a0, zero
; RV32I-FPELIM-NEXT: lw ra, 28(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 32
; RV32I-WITHFP-NEXT: sw zero, -24(s0)
; RV32I-WITHFP-NEXT: sw zero, -28(s0)
; RV32I-WITHFP-NEXT: sw zero, -32(s0)
-; RV32I-WITHFP-NEXT: lui a0, %hi(test1)
-; RV32I-WITHFP-NEXT: addi a1, a0, %lo(test1)
; RV32I-WITHFP-NEXT: addi a0, s0, -28
-; RV32I-WITHFP-NEXT: jalr a1
+; RV32I-WITHFP-NEXT: call test1
; RV32I-WITHFP-NEXT: mv a0, zero
; RV32I-WITHFP-NEXT: lw s0, 24(sp)
; RV32I-WITHFP-NEXT: lw ra, 28(sp)
; RV32I-NEXT: sw ra, 108(sp)
; RV32I-NEXT: sw s0, 104(sp)
; RV32I-NEXT: addi s0, sp, 112
-; RV32I-NEXT: lui a0, %hi(notdead)
-; RV32I-NEXT: addi a1, a0, %lo(notdead)
; RV32I-NEXT: addi a0, s0, -108
-; RV32I-NEXT: jalr a1
+; RV32I-NEXT: call notdead
; RV32I-NEXT: lw a0, -8(s0)
; RV32I-NEXT: lw a0, -8(a0)
; RV32I-NEXT: lw a0, -8(a0)
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a1, %hi(__mulsi3)
-; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: jalr a2
+; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a2, %hi(__mulsi3)
-; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
-; RV32I-NEXT: jalr a2
+; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a1, %hi(__mulsi3)
-; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
; RV32I-NEXT: addi a1, zero, 5
-; RV32I-NEXT: jalr a2
+; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a4, %hi(__muldi3)
-; RV32I-NEXT: addi a4, a4, %lo(__muldi3)
-; RV32I-NEXT: jalr a4
+; RV32I-NEXT: call __muldi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a2, %hi(__muldi3)
-; RV32I-NEXT: addi a4, a2, %lo(__muldi3)
; RV32I-NEXT: addi a2, zero, 5
; RV32I-NEXT: mv a3, zero
-; RV32I-NEXT: jalr a4
+; RV32I-NEXT: call __muldi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: lui a1, %hi(__muldi3)
-; RV32I-NEXT: addi a4, a1, %lo(__muldi3)
; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: srai a3, a2, 31
-; RV32I-NEXT: jalr a4
+; RV32I-NEXT: call __muldi3
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: lui a1, %hi(__muldi3)
-; RV32I-NEXT: addi a4, a1, %lo(__muldi3)
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: mv a3, zero
-; RV32I-NEXT: jalr a4
+; RV32I-NEXT: call __muldi3
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a2, %hi(__umodsi3)
-; RV32I-NEXT: addi a2, a2, %lo(__umodsi3)
-; RV32I-NEXT: jalr a2
+; RV32I-NEXT: call __umodsi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a2, %hi(__modsi3)
-; RV32I-NEXT: addi a2, a2, %lo(__modsi3)
-; RV32I-NEXT: jalr a2
+; RV32I-NEXT: call __modsi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a3, %hi(__lshrdi3)
-; RV32I-NEXT: addi a3, a3, %lo(__lshrdi3)
-; RV32I-NEXT: jalr a3
+; RV32I-NEXT: call __lshrdi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a3, %hi(__ashrdi3)
-; RV32I-NEXT: addi a3, a3, %lo(__ashrdi3)
-; RV32I-NEXT: jalr a3
+; RV32I-NEXT: call __ashrdi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: lui a3, %hi(__ashldi3)
-; RV32I-NEXT: addi a3, a3, %lo(__ashldi3)
-; RV32I-NEXT: jalr a3
+; RV32I-NEXT: call __ashldi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I-FPELIM-NEXT: andi a0, a0, -16
; RV32I-FPELIM-NEXT: sub a0, sp, a0
; RV32I-FPELIM-NEXT: mv sp, a0
-; RV32I-FPELIM-NEXT: lui a1, %hi(notdead)
-; RV32I-FPELIM-NEXT: addi a1, a1, %lo(notdead)
-; RV32I-FPELIM-NEXT: jalr a1
+; RV32I-FPELIM-NEXT: call notdead
; RV32I-FPELIM-NEXT: mv a0, s1
; RV32I-FPELIM-NEXT: addi sp, s0, -16
; RV32I-FPELIM-NEXT: lw s1, 4(sp)
; RV32I-WITHFP-NEXT: andi a0, a0, -16
; RV32I-WITHFP-NEXT: sub a0, sp, a0
; RV32I-WITHFP-NEXT: mv sp, a0
-; RV32I-WITHFP-NEXT: lui a1, %hi(notdead)
-; RV32I-WITHFP-NEXT: addi a1, a1, %lo(notdead)
-; RV32I-WITHFP-NEXT: jalr a1
+; RV32I-WITHFP-NEXT: call notdead
; RV32I-WITHFP-NEXT: mv a0, s1
; RV32I-WITHFP-NEXT: addi sp, s0, -16
; RV32I-WITHFP-NEXT: lw s1, 4(sp)
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
-; RV32I-FPELIM-NEXT: lui a0, %hi(va1)
-; RV32I-FPELIM-NEXT: addi a0, a0, %lo(va1)
; RV32I-FPELIM-NEXT: lui a3, 261888
; RV32I-FPELIM-NEXT: addi a4, zero, 2
; RV32I-FPELIM-NEXT: mv a2, zero
-; RV32I-FPELIM-NEXT: jalr a0
+; RV32I-FPELIM-NEXT: call va1
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
-; RV32I-WITHFP-NEXT: lui a0, %hi(va1)
-; RV32I-WITHFP-NEXT: addi a0, a0, %lo(va1)
; RV32I-WITHFP-NEXT: lui a3, 261888
; RV32I-WITHFP-NEXT: addi a4, zero, 2
; RV32I-WITHFP-NEXT: mv a2, zero
-; RV32I-WITHFP-NEXT: jalr a0
+; RV32I-WITHFP-NEXT: call va1
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
-; RV32I-FPELIM-NEXT: lui a0, %hi(va2)
-; RV32I-FPELIM-NEXT: addi a0, a0, %lo(va2)
; RV32I-FPELIM-NEXT: lui a3, 261888
; RV32I-FPELIM-NEXT: mv a2, zero
-; RV32I-FPELIM-NEXT: jalr a0
+; RV32I-FPELIM-NEXT: call va2
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
-; RV32I-WITHFP-NEXT: lui a0, %hi(va2)
-; RV32I-WITHFP-NEXT: addi a0, a0, %lo(va2)
; RV32I-WITHFP-NEXT: lui a3, 261888
; RV32I-WITHFP-NEXT: mv a2, zero
-; RV32I-WITHFP-NEXT: jalr a0
+; RV32I-WITHFP-NEXT: call va2
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: sw a3, 12(sp)
; RV32I-FPELIM-NEXT: addi a0, sp, 27
; RV32I-FPELIM-NEXT: sw a0, 0(sp)
-; RV32I-FPELIM-NEXT: lui a0, %hi(__adddf3)
-; RV32I-FPELIM-NEXT: addi a5, a0, %lo(__adddf3)
; RV32I-FPELIM-NEXT: addi a0, sp, 19
; RV32I-FPELIM-NEXT: andi a0, a0, -8
; RV32I-FPELIM-NEXT: lw a4, 0(a0)
; RV32I-FPELIM-NEXT: mv a0, a1
; RV32I-FPELIM-NEXT: mv a1, a2
; RV32I-FPELIM-NEXT: mv a2, a4
-; RV32I-FPELIM-NEXT: jalr a5
+; RV32I-FPELIM-NEXT: call __adddf3
; RV32I-FPELIM-NEXT: lw ra, 4(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 32
; RV32I-FPELIM-NEXT: ret
; RV32I-WITHFP-NEXT: sw a3, 4(s0)
; RV32I-WITHFP-NEXT: addi a0, s0, 19
; RV32I-WITHFP-NEXT: sw a0, -12(s0)
-; RV32I-WITHFP-NEXT: lui a0, %hi(__adddf3)
-; RV32I-WITHFP-NEXT: addi a5, a0, %lo(__adddf3)
; RV32I-WITHFP-NEXT: addi a0, s0, 11
; RV32I-WITHFP-NEXT: andi a0, a0, -8
; RV32I-WITHFP-NEXT: lw a4, 0(a0)
; RV32I-WITHFP-NEXT: mv a0, a1
; RV32I-WITHFP-NEXT: mv a1, a2
; RV32I-WITHFP-NEXT: mv a2, a4
-; RV32I-WITHFP-NEXT: jalr a5
+; RV32I-WITHFP-NEXT: call __adddf3
; RV32I-WITHFP-NEXT: lw s0, 16(sp)
; RV32I-WITHFP-NEXT: lw ra, 20(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 48
; RV32I-FPELIM-NEXT: lw a4, 0(a0)
; RV32I-FPELIM-NEXT: addi a0, a3, 4
; RV32I-FPELIM-NEXT: sw a0, 0(sp)
-; RV32I-FPELIM-NEXT: lui a0, %hi(__adddf3)
-; RV32I-FPELIM-NEXT: addi a5, a0, %lo(__adddf3)
; RV32I-FPELIM-NEXT: lw a3, 0(a3)
; RV32I-FPELIM-NEXT: mv a0, a1
; RV32I-FPELIM-NEXT: mv a1, a2
; RV32I-FPELIM-NEXT: mv a2, a4
-; RV32I-FPELIM-NEXT: jalr a5
+; RV32I-FPELIM-NEXT: call __adddf3
; RV32I-FPELIM-NEXT: lw ra, 4(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 32
; RV32I-FPELIM-NEXT: ret
; RV32I-WITHFP-NEXT: lw a4, 0(a0)
; RV32I-WITHFP-NEXT: addi a0, a3, 4
; RV32I-WITHFP-NEXT: sw a0, -12(s0)
-; RV32I-WITHFP-NEXT: lui a0, %hi(__adddf3)
-; RV32I-WITHFP-NEXT: addi a5, a0, %lo(__adddf3)
; RV32I-WITHFP-NEXT: lw a3, 0(a3)
; RV32I-WITHFP-NEXT: mv a0, a1
; RV32I-WITHFP-NEXT: mv a1, a2
; RV32I-WITHFP-NEXT: mv a2, a4
-; RV32I-WITHFP-NEXT: jalr a5
+; RV32I-WITHFP-NEXT: call __adddf3
; RV32I-WITHFP-NEXT: lw s0, 16(sp)
; RV32I-WITHFP-NEXT: lw ra, 20(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 48
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
-; RV32I-FPELIM-NEXT: lui a0, %hi(va3)
-; RV32I-FPELIM-NEXT: addi a3, a0, %lo(va3)
; RV32I-FPELIM-NEXT: addi a0, zero, 2
; RV32I-FPELIM-NEXT: lui a2, 261888
; RV32I-FPELIM-NEXT: lui a5, 262144
; RV32I-FPELIM-NEXT: mv a1, zero
; RV32I-FPELIM-NEXT: mv a4, zero
-; RV32I-FPELIM-NEXT: jalr a3
+; RV32I-FPELIM-NEXT: call va3
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
-; RV32I-WITHFP-NEXT: lui a0, %hi(va3)
-; RV32I-WITHFP-NEXT: addi a3, a0, %lo(va3)
; RV32I-WITHFP-NEXT: addi a0, zero, 2
; RV32I-WITHFP-NEXT: lui a2, 261888
; RV32I-WITHFP-NEXT: lui a5, 262144
; RV32I-WITHFP-NEXT: mv a1, zero
; RV32I-WITHFP-NEXT: mv a4, zero
-; RV32I-WITHFP-NEXT: jalr a3
+; RV32I-WITHFP-NEXT: call va3
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: sw a0, 4(sp)
; RV32I-FPELIM-NEXT: sw a0, 0(sp)
; RV32I-FPELIM-NEXT: lw s1, 20(sp)
-; RV32I-FPELIM-NEXT: lui a1, %hi(notdead)
-; RV32I-FPELIM-NEXT: addi a1, a1, %lo(notdead)
-; RV32I-FPELIM-NEXT: jalr a1
+; RV32I-FPELIM-NEXT: call notdead
; RV32I-FPELIM-NEXT: lw a0, 4(sp)
; RV32I-FPELIM-NEXT: addi a0, a0, 3
; RV32I-FPELIM-NEXT: andi a0, a0, -4
; RV32I-WITHFP-NEXT: sw a0, -16(s0)
; RV32I-WITHFP-NEXT: sw a0, -20(s0)
; RV32I-WITHFP-NEXT: lw s1, 4(s0)
-; RV32I-WITHFP-NEXT: lui a1, %hi(notdead)
-; RV32I-WITHFP-NEXT: addi a1, a1, %lo(notdead)
-; RV32I-WITHFP-NEXT: jalr a1
+; RV32I-WITHFP-NEXT: call notdead
; RV32I-WITHFP-NEXT: lw a0, -16(s0)
; RV32I-WITHFP-NEXT: addi a0, a0, 3
; RV32I-WITHFP-NEXT: andi a0, a0, -4
; RV32I-FPELIM-NEXT: sw a0, 32(sp)
; RV32I-FPELIM-NEXT: lui a0, 688509
; RV32I-FPELIM-NEXT: addi a6, a0, -2048
-; RV32I-FPELIM-NEXT: lui a0, %hi(va5_aligned_stack_callee)
-; RV32I-FPELIM-NEXT: addi a5, a0, %lo(va5_aligned_stack_callee)
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 11
; RV32I-FPELIM-NEXT: addi a2, sp, 32
; RV32I-FPELIM-NEXT: addi a3, zero, 12
; RV32I-FPELIM-NEXT: addi a4, zero, 13
; RV32I-FPELIM-NEXT: addi a7, zero, 4
-; RV32I-FPELIM-NEXT: jalr a5
+; RV32I-FPELIM-NEXT: call va5_aligned_stack_callee
; RV32I-FPELIM-NEXT: lw ra, 60(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 64
; RV32I-FPELIM-NEXT: ret
; RV32I-WITHFP-NEXT: sw a0, -32(s0)
; RV32I-WITHFP-NEXT: lui a0, 688509
; RV32I-WITHFP-NEXT: addi a6, a0, -2048
-; RV32I-WITHFP-NEXT: lui a0, %hi(va5_aligned_stack_callee)
-; RV32I-WITHFP-NEXT: addi a5, a0, %lo(va5_aligned_stack_callee)
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 11
; RV32I-WITHFP-NEXT: addi a2, s0, -32
; RV32I-WITHFP-NEXT: addi a3, zero, 12
; RV32I-WITHFP-NEXT: addi a4, zero, 13
; RV32I-WITHFP-NEXT: addi a7, zero, 4
-; RV32I-WITHFP-NEXT: jalr a5
+; RV32I-WITHFP-NEXT: call va5_aligned_stack_callee
; RV32I-WITHFP-NEXT: lw s0, 56(sp)
; RV32I-WITHFP-NEXT: lw ra, 60(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 64