+2015-06-02 Jim Wilson <jim.wilson@linaro.org>
+
+ PR target/66258
+ * config/aarch64/aarch64.c (aarch64_function_value_regno_p): Change
+ !TARGET_GENERAL_REGS_ONLY to TARGET_FLOAT.
+ (aarch64_secondary_reload): Likewise
+ (aarch64_expand_builtin_va_start): Change TARGET_GENERAL_REGS_ONLY
+ to !TARGET_FLOAT.
+ (aarch64_gimplify_va_arg_expr, aarch64_setup_incoming_varargs):
+ Likewise.
+
2015-06-03 Kugan Vivekanandarajah <kuganv@linaro.org>
Zhenqiang Chen <zhenqiang.chen@linaro.org>
/* Up to four fp/simd registers can return a function value, e.g. a
homogeneous floating-point aggregate having four members. */
if (regno >= V0_REGNUM && regno < V0_REGNUM + HA_MAX_NUM_FLDS)
- return !TARGET_GENERAL_REGS_ONLY;
+ return TARGET_FLOAT;
return false;
}
/* A TFmode or TImode memory access should be handled via an FP_REGS
because AArch64 has richer addressing modes for LDR/STR instructions
than LDP/STP instructions. */
- if (!TARGET_GENERAL_REGS_ONLY && rclass == GENERAL_REGS
+ if (TARGET_FLOAT && rclass == GENERAL_REGS
&& GET_MODE_SIZE (mode) == 16 && MEM_P (x))
return FP_REGS;
vr_save_area_size
= (NUM_FP_ARG_REGS - cum->aapcs_nvrn) * UNITS_PER_VREG;
- if (TARGET_GENERAL_REGS_ONLY)
+ if (!TARGET_FLOAT)
{
if (cum->aapcs_nvrn > 0)
sorry ("%qs and floating point or vector arguments",
&is_ha))
{
/* TYPE passed in fp/simd registers. */
- if (TARGET_GENERAL_REGS_ONLY)
+ if (!TARGET_FLOAT)
sorry ("%qs and floating point or vector arguments",
"-mgeneral-regs-only");
gr_saved = NUM_ARG_REGS - local_cum.aapcs_ncrn;
vr_saved = NUM_FP_ARG_REGS - local_cum.aapcs_nvrn;
- if (TARGET_GENERAL_REGS_ONLY)
+ if (!TARGET_FLOAT)
{
if (local_cum.aapcs_nvrn > 0)
sorry ("%qs and floating point or vector arguments",